Problem Statement: The predominant storage inside a computer systems are on disk

Question

Problem Statement:

The predominant storage inside a computer systems are on disks drives. SCSI disks are

the standard disks in most Unix Workstations from Sun, HP, SGI, and other vendors.

They are also the standard disks in Macintoshes and Higher-end Intel PC's, especially

network servers. Consider the Wide Ultra4 SCSI which transfers data packets in 16-bit

bursts at 160 MHz with a maximum throughput of 320 MB/sec. The data transfers at

higher rates can result in random-noise pulse changes from a 0 to 1 and 1 to a 0. As the

speed of processors and electronic communications increases, these parity flips become

more prevalent and the inability to detect when these errors occur can be fatal. As a

Design Engineer you have been requested to create system for the transmission of these

8-bit packets from an I/O Controller to Memory using Error Correcting Code over 12-bit

data bus line. Wide SCSI contains a 68bit bus; however for the sake of simplification we

are only concerned with the data bits. The other bits in the SCSI bus are for bus

arbitration, synchronization, power management, etc. In this project, we will use even

parity.

Hex Displays Memory I/O Controller

Transmission Vectored Bit: A 4-Bit Parity Vector (P1-P4) are interlaced with the 8-bit

Data Vector (D1:D8):

P1 P2 D1 P3 D2 D3 D4 P4 D5 D6 D7 D8

1) Create an ECC Generator, at the I/O Controller from the 8-bit Data Vector. The output

of the ECC Generator will be the 4-Bit Parity Vector.

2) Construct a 12-bit Data Transmission bus to send the binary data and parity bits over

to Memory.

I just need help woth this second part and it should look something like the middle thing in this image:

https://media.cheggcdn.com/media/b32/b32ff5b2-750f-439e-89e4-9d1b754d063e/phpxTwO0K.png

Explanation / Answer

8 data bits are labeled {a,b,c,d,e,f,g,h}
4 parity bits are labeled {w,x,y,z}

Thesw are positioned into a twelve bit codeword in which the bit positions are numbred from 1 to 12. The parity bits are placed at the positions in which the binary representation for the position has but a single bit set. The data bits are, therefore, placed at positions in which the binary representation for that position has at least two bits set.

The mapping is therefore:


wxaybcdzefgh
------------
123456789ABC (Bit position in HEX)
------------
000000011111 (Binary coding of bit position)
000111100001
011001100110
101010101010
------------


So the four rows of the binary codeings give you the maps for which bits to XOR for each bit in the 4-bit error position value (msb in top row and lsb in bottom row).

When you apply those to your 4-16 decoder, if no bit is in error then all four parity bits will pass and the value applied to the decoder will be 0000. This will turn on channel 0, which is your indication that no error occured. But this also means that this is NOT one of the bits in your error vector. Instead, your error vector is made up of the twelve channels numbered 1 through 12 (just like your codeword bits were numbered).

Now, you don't HAVE to XOR all 12 bits. You can just pull out the eight bits that map to data bits and XOR those with the corresponding eight bits from the received vector to get the corrected vector.

As for how to drive the 3 displays, that depends on what the problem specifies should be displayed under the various conditions.

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