please show whole verilog code, thx Write behavioral Verilog code for a 4-bit co
ID: 3550772 • Letter: P
Question
please show whole verilog code, thx
Write behavioral Verilog code for a 4-bit comparator. Thus comparator should have two 1-bit vector inputs A and B, as well as, one control input sign. The comparator should have three outputs, eq (equals), gt (greater-than), lt (less-than). When sign is 0, the comparison should assume that A and li are unsigned integers, and when sign is 1, it should assume they are 2's complement signed numbers. The behavioral code should use an always statement. You may use if-else, case, or any other statements you find useful, but all code should be contained within one always block.Explanation / Answer
module comparemod (c,a ,b ,equal ,greater ,lower );
output equal ;
reg equal ;
output greater ;
reg greater ;
output lower ;
reg lower ;
input [3:0] a ,b;
input
if(c==0)
begin
if (a<b) begin
equal = 0;
lower = 1;
greater = 0;
end
else if (a==b) begin
equal = 1;
lower = 0;
greater = 0;
end
else begin
equal = 0;
lower = 0;
greater = 1;
end;
end;
else if(c==1)
begin
if (a<b) begin
equal = 0;
lower = 0;
greater = 1;
end
else if (a==b) begin
equal = 1;
lower = 0;
greater = 0;
end
else begin
equal = 0;
lower = 1;
greater = 0;
end;
end;
endmodule;
Explaination:
when c=0, it will do the normal comparison, when c=1 its 2's complement comparison of the binary number given , here we no need to perform the 2's complement calculation. because when we take 2's complement for numbers the greater value become lower and lower become greater.this can be done with out performing twos complement.
for example compare a=1000 and b=0111 in c=0 mode A results greater =1where its treat as unsigned number.
in c=1,the two's complement of a=0111,twos complement of b=1000; whcih results lower=1.
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