1. the size of data bus determines the total size of addressable memory t/f? 2.

Question

1. the size of data bus determines the total size of addressable memory t/f?

2. the size of the address bus in Pentium 4 is ------ bits.

3. intel processor 80286 has-----bit address bus which implies that max addressable memory is ----

4. the 2 types of conditional branch are-----

5.Ram is -----memory a. volatile b. non volatile

6. cycle time for RAM is about----and for flash memory is-------

  a. 10 ns, 20ns  b. 10ns, 80ns c. 20nc, 10ns d 100ns,100ns  e none

7 the paging was introduced by intel with its IA architecture with the -----processor

8. if a system uses a 2.0 GHz clock, then the clock period is :

    a. 1.5 ns   b. 0.50 ns   c. 1.0 ns    d 2ns    e none of the above

9. processor is normally executing the-------cycle forever

10. the two basic classes of RAM dynamic RAM and -----RAM

Explanation / Answer

1) size of data bus determines the total size of addressable memor

2).36 bits

3)The Intel 80286 (often called simply the 286) was a 16-bit microprocessor ,The 80286 chip contained a 24-bit address bus

4)compare instructions and conditional branch instructions

5)Ram is volatile memory

6)cycle time is the time, usually measured in nanosecond s, between the start of one random access memory ( RAM ) access to the time when the next access can be started.

10 ns, 20ns

20nc, 10ns

7)A-64

IA-64 is the name of the Instruction Set Architecture (ISA). It's an actual concrete specification; you'll be able to go out and buy a book on IA-64, just like you can on the x86 architecture. IA-64 specifies a computing architecture (an instruction set, an instruction format, registers, etc.) that implements the ideas embodied in the EPIC design philosophy

8) b. 0.50 ns

9)burst cycle

10) static RAM

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