I Definately need help with this chache Question set! We have a memory system wi

Question

I Definately need help with this  chache Question set!

We have a memory system with 32 bits address space, a cache of 4k entries and the block size of 8 words. Draw the cache organization diagram similar to the one in the figure below. [8] How many bits does each entry of the cache have? [4] How many bytes does the entire cache have? [4] If we decide to use write-back policy, explain what change must be made to the cache design? [4] Consider the three organizations of the memory system in Figure 2 below. A memory address request takes 1 cycle. Memory Access takes 15 cycles, and 1 cycle to read data from the bus. What are the miss penalties for these three organizations, respectively, if die block size = 256 words? [5] If the cost of producing the base system, the one-word-wide memory in text figure 5.11 (see figure below), is S100. Adding an extra memory port (bank) of 32 bits cost $15 and adding a set of 32-bit data lines (bus) costs $2. If you want to design a memory system with block size = 256 words that costs no more than $200 in total, what is the best organization that minimizes the miss penalty within the given budget constraint? In this question, you need to determine the optimal number of ports, m. and the optimal number of bus sets. b. of bus lines. Show your work by steps. [9] 2.3 What is the minimum miss penalty of the optimal design in question 2.2? [1]There are three (3) caches, each consisting of eight (8) one-word blocks. The first cache is direct mapped, the second is two-way set associative, and the third is four-way associative. Assume that each block holds its own memory address, and the replacement policy used is least recently used. For each of the three caches, fill out the cache contents and indicate the hit or miss after each reference, respectively. Note, the content at address a is represented in (a). you can also just write the address a in the table.

Explanation / Answer

P = processor

C = cache memory

X = bus transceiver

M = main memory

P P P P P P P P P P P P P P P P

C C C C C C C C C C C C C C C C

X X X X X X X X X X X X X X X X

?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ??

M

??

Shared

bus

Figure 1.2: Shared memory multiprocessor with caches

we can use n number of catch which can easly satisfy 256word

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