How fast can the below circuit be clocked? Check whether it would meet the hold

Question

How fast can the below circuit be clocked? Check whether it would meet the hold time constraints. Assume the D-Q flip flip used in the circuit has the following timing characteristics

Setup time = 0.5 ns

Hold time = 0.3 ns

tcQ = 0.6ns (min) to 1.2ns(max)

Assume a 2-input AND gate has a delay of 1.3ns, a 2-input XOR gate has a delay of 1.5ns and an inverter a delay of 1ns

How fast can the below circuit be clocked? Check whether it would meet the hold time constraints. Assume the D-Q flip flip used in the circuit has the following timing characteristics Setup time = 0.5 ns Hold time = 0.3 ns tcQ = 0.6ns (min) to 1.2ns(max) Assume a 2-input AND gate has a delay of 1.3ns, a 2-input XOR gate has a delay of 1.5ns and an inverter a delay of 1ns

Explanation / Answer

Tmin = 2n+ .5n+.3n+1.2n+1.3n+1.5n+2n+1n+2n=7.8n

f=1/7.8n=128.2MHz

Had the clock delays were different the timing would have been different. The about circuit takes minimum of 7.8ns delay.

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