A. 1. Create a Verilog HDL file for a 4-bit adder and add it to the project A. 2
ID: 2990483 • Letter: A
Question
A. 1. Create a Verilog HDL file for a 4-bit adder and add it to the project
A. 2.Create a Verilog HDL file for the decoder 1 and add it to the project
A. 3.create the 4-bit Binary to Seven Segment decoder and add it to the project
A. 4. Create a Verilog HDL file for the top level cirduit and add it to the project
As shown in Fig. 2, the system you will build consists of a 4-bit adder, a decoder that converts 5-bit addition result into two hexadecimal digits, and a 4-bit binary to seven segment decoder. 4-bit unsigned numbers range from 0 to 15. Thus, the addition results will range from 0 to 31. To show the addition results in two hexadecimal digits, a logic is needed to convert the 5-bit result (including a 4-bit sum and a 1-bit carry-out) to two 4-bit binary, one for the tens digit and the other for the ones digit Finally, the two 4-bit binary data will each connect to the inputs of a 4-bit Binary to Seven Segment decoder that you built in Lab3a.Explanation / Answer
//top module
module top(input [3:0]A, input[3:0]B,input carryin, output reg[6:0] tens_digit , output reg[6:0] units_digit);
wire [3:0]F,I1,I2,in;
wire carryout;
adder_4_bit u1 ( A, B, carryin, F, carryout);
decoder_1 u2 ( F, carryout, I1, I2 );
seven_segment_display u3 (I1 , tens_digit);
seven_segment_display u4 ( I2, units_digit );
endmodule
//adder module
module adder_4_bit (input [3:0]A , input [3:0]B, input carryin, output [3:0]F, output carryout ) ;
assign {carryout , F} = A + B + carryin ;
endmodule
//decoder_1 module
module decoder_1 (input [3:0]F, input carryout, output [3:0]I1, output [3:0]I2);
assign I1 = {3'b000 , carryout);
assign I2 = F;
endmodule
// 4 bit binary to seven segment converter
module seven_segment_display (input [3:0]in , output reg [6:0] out);
always @ (in)
case (in)
0:
out <= 7'b0111111;
1:
out <= 7'b0000110;
2:
out <= 7'b1011011;
3:
out <= 7'b1001111;
4:
out <= 7'b1100110;
5:
out<= 7'b1101101;
6:
out <= 7'b1111101;
7:
out <= 7'b0000111;
8:
out <= 7'b1111111;
9:
out <= 7'b1101111;
10:
out <= 7'b1110111;
11:
out <= 7'b1111100;
12:
out<= 7'b0111001;
13:
out<= 7'b1011110;
14:
out<= 7'b1111001;
15:
out<= 7'b1110001;
endcase
endmodule
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