Question 1 (3 points) Figure 8-3 The circuit shown in Figure 8-3 represents a(n)

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Question 1 (3 points)

Figure 8-3

The circuit shown in Figure 8-3 represents a(n) ________.

Question 1 options:

synchronous BCD decade counter

BCD-to-decimal decoder

synchronous four-bit binary counter

asynchronous BCD decade counter

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Question 2 (4 points)

A MOD 12 and a MOD 10 counter are cascaded. The input clock frequency is 60 MHz. Determine the counter output frequency.

Question 2 options:

1,500 kHz

5 MHz

6 MHz

500 kHz

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Question 3 (3 points)

What is the output state of a MOD-64 counter after 92 input pulses if the starting state is 000000?

Question 3 options:

0101102

0111102

1001002

0111002

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Question 4 (3 points)

Which of the following best describes the characteristics of a MOD-16 counter?

Question 4 options:

Sixteen possible counts, a maximum count of 1510, and frequency division by a factor of eight

Eight possible counts, a maximum count of 710 and frequency division by a factor of eight

Eight possible counts, a minimum count of 710, and frequency division by a factor of sixteen

Sixteen possible counts, a maximum count of 1510, and frequency division by a factor of sixteen

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Question 5 (4 points)

For the circuit shown above, what would be the values of Q output of the Flip-Flop-2 (FF2) during times t3and t5?

Question 5 options:

0 and 0 respectively

0 and 1 respectively

1 and 0 respectively

1 and 1 respectively

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Question 6 (3 points)

Four positive edge-triggered D flip-flops are used to store a 4-bit binary number as shown here. Determine if the circuit is functioning properly, and if not, what might be wrong.

Question 6 options:

The circuit is functioning properly.

Q2 is incorrect; the flip-flop is probably bad.

A bad connection probably exists between ff-3 and ff-4, causing ff-3 not to reset.

The input to flip-flop 3 (D2) is probably wrong; check the source of D2.

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Question 7 (4 points)

How many flip-flops are required to design a MOD-56 counter?

Give the result as integer number.

Question 7 options:

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Question 8 (4 points)

The figure above shows an integrated 3 bits synchronous counter with synchronous load. An automatic reload is used to reset the count. What type of counter is it?

Question 8 options:

MOD-3

MOD-5

MOD-6

MOD-8

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Question 9 (3 points)

In a MOD-10 counter we can distinguish ______ different states.

Question 9 options:

Four

Nine

Ten

Sixteen

None of the above

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Question 10 (3 points)

Which of the following is one of the primary functions performed by registers?

Question 10 options:

NOR

AND

XOR

memory

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Question 11 (3 points)

Bidirectional shift registers can shift data either right or left.

Question 11 options:

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Question 12 (3 points)

Figure 9-2

Refer to the Shift-Register circuit and waveforms in Figure 9-2. What is the value of the data stored in Q3, Q2, Q1 and Q0 respectively at time 'X'?

Question 12 options:

0 1 0 1

0 1 1 0

1 1 1 0

0 1 1 1

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Question 13 (3 points)

Figure 9-3

Which of the DATA OUT waveforms in Figure 9-3 is correct?

Question 13 options:

DATA OUT a.

DATA OUT d.

DATA OUT b.

DATA OUT c.

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Question 14 (3 points)

Figure 9-4

What type of register is shown in Figure 9-4?

Question 14 options:

Serial/parallel-in parallel-out register.

Parallel-access shift register.

Serial-in parallel-out register.

Parallel-in parallel-out register.

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Question 15 (3 points)

Figure 9-4

Referring to Figure 9-4, what action takes place during the period marked 'W' on the timing diagram?

Question 15 options:

The register has gone into the counter mode and is counting the value of the parallel data previously stored on the parallel inputs.

The register has just been cleared and the clock pulses are being toggled through the register.

The data is shifted from the parallel inputs to the parallel outputs.

Data is being serially shifted through the register.

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Question 16 (3 points)

Figure 9-5

What type of device is shown in Figure 9-5?

Question 16 options:

Parallel-in parallel-out shift register with bidirectional data flow.

4-bit bidirectional universal shift register.

2-bit serial-in 4-bit parallel-out bidirectional shift register.

2-way parallel-in serial-out bidirectional register.

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Question 17 (3 points)

Figure 9-5

Referring to Figure 9-5, what action takes place during the interval labeled 'Z' on the timing diagram?

Question 17 options:

Data is shifted right through the register.

Serial data is entered into the register.

Data is shifted left through the register.

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Question 18 (3 points)

Figure 9-5

Referring to the Function Table in Figure 9-5, taking the CLEAR, S1 and S0 inputs all HIGH will do what?

Question 18 options:

It will cause the parallel data inputs to be loaded and passed to the parallel data outputs.

It will inhibit the operation of the register.

It will reset the parallel registers and inhibit the serial data inputs.

The exact response will depend on what values are loaded into the parallel data inputs.

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Question 19 (4 points)

A serial data path needs a 2000 ns delay. Which output from the circuit (Shift-Register) below will provide the correct delay? Assume that the data is presented to the inputs right before the rising edge of the clock and also the propagation time of the internal flip-flops is very small.

Question 19 options:

Q0

Q1

Q4

None of the above

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Question 20 (3 points)

What type of register accepts data inputs one bit at a time and outputs all its data bits at the same time?

Question 20 options:

Serial in/Serial out

Serial in/Parallel out

Parallel in/Serial out

Parallel in/Parallel out

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synchronous BCD decade counter

BCD-to-decimal decoder

synchronous four-bit binary counter

asynchronous BCD decade counter

Explanation / Answer

Question 14.    Serial/Parallel in , Parallel Out. Parallel Load

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