Using the 0.25 ?m CMOS technology introduced in Chapter 2, design a static CMOS

Question

Using the 0.25 ?m CMOS technology introduced in Chapter 2, design a static CMOS
inverter that meets the following requirements:

a. Matched pull-up and pull-down times (i.e., tpHL = tpLH).

b. tp = 4 nsec (+/- 0.1 nsec).

The load capacitance connected at the output is equal to 5 pF. Notice that this capacitance
is substantially larger than the intrinsic capacitances of the gate. Determine the W and L
of the transistors. To reduce the parasitics, use minimal lengths (L = 0.25 ?m) for all
transistors. Verify and optimize the design using ADS after proposing a first design using
manual computations. Compute also the energy consumed per transition.

Explanation / Answer

tpHL = 0.7 x R x Cout = 0.7 x Rn x (L/W) x Cout = 4ns

=> 0.7 x 12.5 x 10^3 x (.25/W) x 5 x 10^-12 = 4x 10^-9

=> Wn = 2.73 um

tpHL = tpLH => Rn x (Ln/Wn) = Rp x (Lp/Wp)

=> Wp = 30/12.5 x 2.73 um = 6.56um(ans)

Thank you.

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