The picture i posted is the Traffic Light Controller.pdf (project file:project r
ID: 2988120 • Letter: T
Question
The picture i posted is the Traffic Light Controller.pdf (project file:project requirement).It also include a file called timer10.v,i will post the code under this line.I actually don't know what it is.
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So,that's all i got to say for you guys and really thanks for you guys help,
This is the project that i have to finish ,please help me finish it .
By the way we are using the Quartus II v13 Web Edition software in the laboratory.So, you need to use this software to finish this project and please test it really works.
When i received you project, i will test it to see whether it works or not. My email: hellojeff2014@gmail.com //Please send all you file to this mailbox.
Thank you.Have a great day!
You will need to use your problem solving skills, your Verilog skill, you knowledge of finite state machines, and your experience with the UP2 boards and Quartus to complete this project.Explanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity traffic is
port (clk: in STD_LOGIC;
clr: in STD_LOGIC;
lights: out STD_LOGIC_VECTOR(5 downto 0));
end traffic;
architecture traffic of traffic is
type state_type is (s0, s1, s2, s3, s4, s5);
signal state: state_type;
signal count: STD_LOGIC_VECTOR(3 downto 0);
constant SEC5: STD_LOGIC_VECTOR(3 downto 0) := "1111";
constant SEC1: STD_LOGIC_VECTOR(3 downto 0) := "0011";
begin
process(clk, clr)
begin
if clr = '1' then
state <= s0;
count <= X"0";
elsif clk'event and clk = '1' then
case state is
when s0 =>
if count < SEC5 then
state <= s0;
count <= count + 1;
else
state <= s1;
count <= X"0";
end if;
when s1 =>
if count < SEC1 then
state <= s1;
count <= count + 1;
else
state <= s2;
count <= X"0";
end if;
when s2 =>
if count < SEC1 then
state <= s3;
count <= count + 1;
else
state <= s3;
count <= X"0";
end if;
when s3 =>
if count < SEC5 then
state <= s3;
count <= count + 1;
else
state <= s4;
count <= X"0";
end if;
when s4 =>
if count < SEC1 then
state <= s4;
count <= count + 1;
else
state <= s5;
count <= X"0";
end if;
when s5 =>
if count < SEC1 then
state <= s5;
count <= count + 1;
else
state <= s0;
count <= X"0";
end if;
when others =>
state <= s0;
end case;
end if;
end process;
C2: process(state)
begin
case state is
when s0 => lights <= "100001";
when s1 => lights <= "100010";
when s2 => lights <= "100100";
when s3 => lights <= "001100";
when s4 => lights <= "010100";
when s5 => lights <= "100100";
when others => lights <= "100001";
end case;
end process;
end traffic;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity clkdiv is
port(
mclk : in STD_LOGIC;
clr : in STD_LOGIC;
clk190 : out STD_LOGIC;
clk3 : out STD_LOGIC
);
end clkdiv;
architecture clkdiv of clkdiv is
signal q:STD_LOGIC_VECTOR(24 downto 0);
begin
process(mclk, clr)
begin
if clr = '1' then
q <= X"000000" & '0';
elsif mclk'event and mclk='1' then
q <= q + 1;
end if;
end process;
clk3 <= q(24); -- 3 Hz
clk190 <= q(18); -- 190 H
end clkdiv;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity traffic_lights_top is
port(
clk : in STD_LOGIC;
btn : in STD_LOGIC_VECTOR(3 downto 3);
ld : out STD_LOGIC_VECTOR(7 downto 2)
);
end traffic_lights_top;
architecture traffic_lights_top of traffic_lights_top is
component clkdiv is
port(
mclk : in STD_LOGIC;
clr : in STD_LOGIC;
clk190 : out STD_LOGIC;
clk3 : out STD_LOGIC
);
end component;
component traffic is
port (clk: in STD_LOGIC;
clr: in STD_LOGIC;
lights: out STD_LOGIC_VECTOR(5 downto 0));
end component;
signal clr, clk3: STD_LOGIC;
begin
clr <= btn(3);
U1: clkdiv
port map (
mclk=>clk,
clr=>clr,
clk3=>clk3
);
U2: traffic
port map (
clk=>clk3,
clr=>clr,
lights=>ld
);
end traffic_lights_top;
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