****** I need this to be done in vhdl********* Design the 4-bit Arithmetic Logic
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Question
****** I need this to be done in vhdl*********
Design the 4-bit Arithmetic Logic Unit (ALU) shown in the figure below. A (4-bit), B (4-bit), Opcode (2-bit), and Mode (1-bit) are the inputs; and ALUOut (4-bit) and Cout (1-bit) are the outputs of the design. A and B hold the values of the operands. Mode and Opcode together indicate the type of the operation performed by ALU
Components:
? Design the Arithmetic Unit that consists of one 4-bit adder and one 2-bit multiplier. The
two least significant bits of A and B are used as inputs of the multiplier. The output will be 4-bit.
? Design a 4-bit Logic Unit which performs the following operations: A and B, A or B, A nand B, A nor B.
? Design a 4-bit Shifter unit with A, B, and Direction as inputs and ShifOut as output. The value of A should be shifted by the value specified in B. The
Explanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALUcontroller is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
opcode : in STD_LOGIC_VECTOR (1 downto 0);
mode : in STD_LOGIC;
ALU_OUT : out STD_LOGIC_VECTOR (3 downto 0);
cout: out STD_LOGIC);
end ALUcontroller;
architecture Behavioral of ALUcontroller is
component Arthimatic is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC;
out1 : out STD_LOGIC_VECTOR (3 downto 0);
carry:out STD_LOGIC
);
end component;
component shifter is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC;
out3 : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component mux is
port(
s : in std_logic;
d0 : in std_logic_vector(3 downto 0);
d1 : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0)
);
end component;
component Logical is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
out2 : out STD_LOGIC_VECTOR (3 downto 0);
opcode : in STD_LOGIC_VECTOR (1 downto 0)
);
end component;
signal direction : STD_LOGIC;
signal opc : STD_LOGIC_VECTOR (1 downto 0);
signal sel0,sel1,sel2 : STD_LOGIC;
signal AR_out,Lo_out,Shift_out,Mux_out:STD_LOGIC_VECTOR (3 downto 0);
begin
sel0<=mode;
sel1<=opcode(1);
sel2<=opcode(0);
lo:logical port map(A=>A,B=>B,opcode=>opcode,out2=>Lo_out);
Arth:Arthimatic port map(A,B,sel2,AR_out);
shift:shifter port map(A,B,sel2,Shift_out);
mux1:mux port map(sel1,Ar_out,Shift_out,Mux_out);
mux2:mux port map(sel0,Mux_out,Lo_out,ALU_out);
end Behavioral;
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