Build a Top Schematic to Test on the Basys 3 Board As with our previous assignme

Question

Build a Top Schematic to Test on the Basys 3 Board As with our previous assignment, we must create a top schematic to test our myALU as a component. Create a new VHD source file named myALU_top. Set the inputs and outputs to have all the switches as inputs, and all the LEDs as outputs. Bring in a component of your myALU and instantiate it and portmap the inputs of the top (the switches and LEDs) to the components inputs and outputs. Refer to Figures 4 and 5 to see how to map the appropriate switches and LEDs to the appropriate inputs using signals. Notice that the signals for all the flag bits are individual assignments of a STD_LOGIC_VECTOR signal named "led(7 downto 4)" Figure 4. The entity of the top schematic. This x-ray view shows an instance of the myALU component and how to name your signals such that the outputs work on the board.

Explanation / Answer

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity myALU_top is
Port ( SW : in STD_LOGIC_VECTOR (15 downto 0);
LED : out STD_LOGIC_VECTOR (15 downto 0));
end myALU_top;

architecture Behavioral of myALU_top is
component myALU
port(A,B: in STD_LOGIC_VECTOR (3 downto 0);
Operand: in STD_LOGIC_VECTOR (1 downto 0);
   Zero,Overflow,Negative,Carryout:out STD_LOGIC;
   Dataout:out STD_LOGIC_VECTOR (3 downto 0));
end component;

begin
U1:myALU port map(
A => SW(15 downto 12),
                       B => SW(11 downto 8),
           Operand => SW(2 downto 0),
                   Zero => LED(7),
               Overflow => LED(6),
               Negative => LED(5),
               Carryout => LED(4),
               Dataout => LED(3 downto 0));
  
       LED(15 downto 12)<=SW(15 downto 12);
LED(11 downto 8)<=SW(11 downto 8);      

end Behavioral;

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