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Write a test bench for the sequence detector given below: library IEEE; use IEEE

ID: 2319746 • Letter: W

Question

Write a test bench for the sequence detector given below: library IEEE; use IEEE std logic 1164 all; entity sequence detector is port clk: in STD LOGIC; rst: in STD LOGIC; x: in STD LOGIC; z: out STD LOGIC); end sequence detector; architecture sequence detector arch of sequence detector is type seq detect type is (S1, S2, S3, S4: signal seq detect: seq detect type: begin seq detect machine: process (clk begin if clk event and clk '1' then if rst '1' then seq detect S1; else case seq detect is when S1 if x 1' then seq detect S2; elssifx '0' then seq detect S1 end if when S2 if '1' then seq detect S3; elsifx '0' then seq detect S1: end if when S3 if x '1' then seq detect S3; elsif x 'O' then seq detect S4; end if

Explanation / Answer

The Sequece Detector Detect the sequence of 1101 and when this sequence is detected the output z becomes 1

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity tb_sequence_detector is
end tb_sequence_detector;

architecture behavior of tb_sequence_detector is

signal clk,rst,x,z : std_logic := '0';
constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: entity work.sequence_detector PORT MAP (
clk => clk,
rst => rst,
x => x,
z => z
);

-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;


stim_proc: process
begin
x <= '1'; --1
wait for clk_period;
x <= '1'; --11
wait for clk_period;
x <= '0'; --110
wait for clk_period;
x <= '1'; --1101
wait for clk_period;
x <= '1'; --11011
wait for clk_period;
x <= '1'; --110111
wait for clk_period;
x <= '0'; --1101110
wait for clk_period;
x <= '1'; --11011101
wait for clk_period;
x <= '0'; --110111010
wait for clk_period;
x <= '1'; --1101110101
wait for clk_period;
x<='1' --11011101011
wait for clk_period;
x<='0' --110111010110
wait for clk_period;
x<='1' --1101110101101
rst<='1' --reset the sequence
wait for clk_period;
x <= '1'; --1
wait for clk_period;
x <= '1'; --11
wait for clk_period;
x <= '0'; --110
wait for clk_period;
x <= '1'; --1101
wait;   
end process;

END;

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