The diagram shows an 8-bit-wide data bus that transfers data between a microproc

Question

The diagram shows an 8-bit-wide data bus that transfers data between a microprocessor and memory. Data on this bus is determined by the control signals mRead and mWrite. When mRead = '1', the data on the memory's internal bus 'membus' is output to the data bus. When mWrite = '1', the data on the processor's internal bus 'probus' is output to the data bus. When both control signals are '0', the data bus must be in a high-impedance state. Write VHDL statements to represent the data bus. Normally mRead = mWrite = '1' does not occur. But if it occurs, what value will the data bus take?

Explanation / Answer

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;         
use ieee.std_logic_unsigned.all;

entity MemoryMicro is
port(Data: out std_logic_vector(7 downto 0);
mwrite:in std_logic;
mread:in std_logic;
membus:in std_logic_vector(7 downto 0);
probus:in std_logic_vector(7 downto 0));
end MemoryMicro;
architecture Behav of MemoryMicro is
signal control:std_logic_vector(1 downto 0);
begin
process(mwrite,mread)
begin
control<=mread&mwrite;
case control is

   when "00" =>   Data<= "00000000";
   when "01" =>   Data <= membus;
   when "10" =>   Data<= probus;
   when others =>   Data<= "ZZZZZZZZ";
end case;
end process;
end Behav;

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