The following circuit is a 4-bit parallel/serial load shift register with enable

Question

The following circuit is a 4-bit parallel/serial load shift register with enable input. Shifting operation: s_1-0. Parallel load: s_1- 1. Note that Q = Q_3Q_2Q_1Q_0. D = D_3D_2D_1D_0 Write a structural VHDL code. You MUST create a file for: i) flip flop, ii) MUX 2-to-1, and iii) top file (where you will interconnect the flip flops and MUXes). Provide a printout. Write a VHDL test bench according to the timing diagram shown below. Complete the timing diagram by simulating your circuit (Timing Simulation). The dock frequency must be 50 MHz with 50% duty cycle. Provide a printout

Explanation / Answer

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Code VHDL - [expand]

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  library IEEE;  use IEEE.std_logic_1164.all;  use work.dff;     entity bitreg4 is     port (Clk_sig: in std_logic;        Load : in std_logic;        --D : in std_logic_vector(1 to 4);        D_sig : in std_logic_vector(1 to 4);        Q_sig : out std_logic_vector(1 to 4));          end bitreg4;     architecture bhv of bitreg4 is  begin  Dff1 : entity work.dff port map (d => D_sig(1), preset => '0', clear => '1', clk => Clk_sig,q => Q_sig(1));  Dff2 : entity work.dff port map (d => D_sig(2), preset => '0', clear => '1', clk => Clk_sig,q => Q_sig(2));  Dff3 : entity work.dff port map (d => D_sig(3), preset => '0', clear => '1', clk => Clk_sig,q => Q_sig(3));  Dff4 : entity work.dff port map (d => D_sig(4), preset => '0', clear => '1', clk => Clk_sig,q => Q_sig(4));     process(Clk_sig,D_sig,Load)  begin  if Load = '1' then    Q_sig <= D_sig;        end if;  end process;  end bhv;  

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  library IEEE;  use IEEE.std_logic_1164.all;      entity dffv3 is      port(                  D       : in    std_logic;                  clk     : in    std_logic;                  Qbar    : out   std_logic;                  Q       : out   std_logic          );    end dffv3;      architecture bhav of dffv3 is    begin      -- Your VHDL code defining the model goes here    process (d, clk)    begin           -- clock rising edge          if (clk'event and clk='1') then                  q <= d;                  Qbar <= not d;          end if;    end process;      end bhav;  

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