5. PVT variation [10 pts] What combination of V corner (low V or high V), temper

Question

5. PVT variation [10 pts] What combination of V corner (low V or high V), temperature (high or low) and supply noise condition (+10% or-10%) should you use to simulate each of the following circuit specifications? We are interested in the worst case. Explain your answers. (a) [2 pts] Leakage power of a logic gate (b) [2 pts] Cycle time of a pipeline circuit (c) [3 pts] Logic delay causing min delay issue in a pipeline circuit (d) [3 pts] Domino gate static noise margin (hint: consider DIBL, Drain-Induced-Barrier Lowering)

Explanation / Answer

a.lekage power of logic circuit.....low vt.....because in fast corner vt is less hence current is more....

high temperature ........becuase vt is inveresly related to temperature.

+10% supply.....more supply means more lekage current..power=v*i.

b. cycle time of pipeline circuit... high vt.... becuase for slow corner vt is high which will affect the performance of operation for circuit

low temp....becuase for low temp we will get worst performance time of operation

-10% supply....becuase for less supply noise circuit operation becomes affeced more

c.logic dealy in min dealy issue in logic circuit... high vt.....as for slow corner we will get worst(minimum) delay for circuit

low temperature....as it is again related to vt......vt is inversely related to temp..

+10% supply.....we will get maximum delay in this range...

d. Domino gate static noise margin (DIBL)....low vt....due to DIBL effect

low temperature.........DIBL effect is more related to temperature.....

+10% supply.......more supply noise means more noise we will see.

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