3. MOS capacitance [12 pts] A PMOS device whose source, drain, and body terminal

Question

3. MOS capacitance [12 pts] A PMOS device whose source, drain, and body terminals are tied together is connected to an ideal capacitor. The PMOS device has a sub-threshold swing of2x0.026xln10 [V/dec] and a |Vi of0.5V Ignore the gate-to-source and gate-to-drain overlap capacitances. If Vn is initialized to OV and a 1.0V high-to-low signal is applied, Vn is boosted down to -0.5V via the capacitive coupling effect. What would the Vv voltage be after the boosting if the initial Vv voltage is 1.0V instead of 0v? 1.0V ov VN

Explanation / Answer

As when the VN=0V initially,

And as 1V high to low signal is applied , VN =-0.5V = (0-1)/2 V

That means the ideal capacitance and the Capacitance from MOS is equal.

When VN=1V initially,

And as 1V high to low signal is applied , VN =1 + (0 -1)/2 V= 0.5V

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