Question 3 VHDL (25 marks) a. (5 marks) The entity for a 2:1 multiplexer is give

Question

Question 3 VHDL (25 marks) a. (5 marks) The entity for a 2:1 multiplexer is given below. Write the corresponding architecture in behavioural VHDL library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux2 is port (10, il, s: in std_logic; y: out std logic); end mux2; b. (10 marks) Write an entity-architecture pair for a 4:1 multiplexer using only the "mux2" devices in part a. This multiplexer will have a 2 bit select input to multiplex one of 4 inputs to a single output. The name of the entity should be "mux4". Make sure to declare "mux2" as a component and also make sure that the description is a structural one (zero marks will be awarded for a behavioural description). c. (10 marks) Write an entity-architecture pair for a falling edge-triggered 32-bit synchronous binary up counter with synchronous reset in VHDL. The counter must have a single clock input named clk, a reset input named rst and a std_logic_vector output named q. Marks will be deducted for solutions which are excessively complex or long. Hint: use a behavioural description.

Explanation / Answer

vhdl program for 2 to 1 mux
The 2-to-1 Mux can be designed with one OR gate, two
-- AND gates, and one Inverter. Such realization of the
-- circuit is shown on Teahlab.com. The circuit is
-- interactive; so you may verify it.
--
-- Teahlab takes a structural approach to the VHDL
-- design of the 2-to-1 Mux. Hence, we design the
-- circuit in two stages:

-- In stage one we define three basic entities:
-- AND, OR, NOT.
-- In stage two we use the basic entities to construct
-- the Mux.
--
-- One of the advantages of structural designs is that
-- from the VHDL program you can tell what the physical
-- circuit looks like.
--
-- It is very important to learn structural design (RTL)
-- strategies because as your assignments become larger
-- and larger, knowledge of register transfer level
-- (RTL) design strategies become indispensable.
------------------------------------------------------------
-- This is the AND gate
library ieee;
use ieee.std_logic_1164.all;
entity andGate is
port( A, B : in std_logic;
F : out std_logic);
end andGate;
architecture func of andGate is
begin
F <= A and B;
end func;
--*============================
-- This is the OR gate
library ieee;
use ieee.std_logic_1164.all;
entity orGate is
port( A, B : in std_logic;
F : out std_logic);
end orGate;
architecture func of orGate is
begin
F <= A or B;
end func;
--*============================
-- This is the NOT gate
library ieee;
use ieee.std_logic_1164.all;
entity notGate is
port( inPort : in std_logic;
outPort : out std_logic);
end notGate;
--
architecture func of notGate is
begin
outPort <= not inPort;
end func;
--*=======================*=====================
-- Now we write the definition for the 2-to-1 Mux
library ieee;
use ieee.std_logic_1164.all;
entity Mux_2_to_1 is
port( D0, D1, S : in std_logic;
F : out std_logic);
end Mux_2_to_1;
--
architecture Func of Mux_2_to_1 is
component andGate is --import AND Gate entity
port( A, B : in std_logic;
F : out std_logic);
end component;

component orGate is --import OR Gate entity
port( A, B : in std_logic;
F : out std_logic);
end component;
component notGate is --import NOT Gate entity
port( inPort : in std_logic;
outPort : out std_logic);
end component;
signal andOut1, andOut2, invOut: std_logic;
begin
-- Just like the real circuit, there
-- are four components: G1 to G4
G1: notGate port map(S, invOut);
G2: andGate port map(invOut, D0, andOut1);
G3: andGate port map(S, D1, andOut2);
G4: orGate port map(andOut1, andOut2, F); -- F
end Func;
---------------------------------------------------------END
---------------------------------------------------------END
Test Bench:
-import std_logic from the IEEE library
library ieee;
use ieee.std_logic_1164.all;
--
entity Mux_2_to_1_tb is
end Mux_2_to_1_tb;
--
architecture tb of Mux_2_to_1_tb is
component Mux_2_to_1 is
port( D0, D1, S : in std_logic;
F : out std_logic);
end component;
signal D0, D1, S, F : std_logic;
begin
mapping: Mux_2_to_1 port map(D0, D1, S, F);
--Concurrent processes: using concurrency usually reduce
--the length of a test bench.
process
begin
S <= '1';
wait for 10 ns;
S <= '0';
wait for 10 ns;
end process;
process
variable errCnt : integer := 0;
begin
--The "assert" keyword allows you to test certain
--conditions. In other words, the point of assertion is
--to allow you to inspect what you expect.
--TEST 1
D0 <= '0';
D1 <= '1';
wait for 15 ns;
if(S = '0') then
assert(F = '0') report "Error 2" severity error;
else
assert(F = '1') report "Error 2" severity error;
end if;
--TEST 2
D0 <= '1';
D1 <= '0';
wait for 15 ns;
if(S = '0') then
assert(F = '1') report "Error 2" severity error;
else
assert(F = '0') report "Error 2" severity error;
end if;
--------------------------------------------------
end process;
end tb;
------------------------------------------------------------
configuration cfg_tb of Mux_2_to_1_tb is
for tb
end for;
end cfg_tb;
---------------------------------------------------------END
---------------------------------------------------------END

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity mux_4to1 is

port(

A,B,C,D : in STD_LOGIC;

S0,S1: in STD_LOGIC;

Z: out STD_LOGIC

);

end mux_4to1;

architecture bhv of mux_4to1 is

begin

process (A,B,C,D,S0,S1) is

begin

if (S0 ='0' and S1 = '0') then

Z <= A;

elsif (S0 ='1' and S1 = '0') then

Z <= B;

elsif (S0 ='0' and S1 = '1') then

Z <= C;

else

Z <= D;

end if;

end process;

end bhv;

VHDL TestBench Code for 4 to 1 Multiplexer

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY tb_mux IS

END tb_mux;

ARCHITECTURE behavior OF tb_mux IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT mux_4to1

PORT(

A : IN std_logic;

B : IN std_logic;

C : IN std_logic;

D : IN std_logic;

S0 : IN std_logic;

S1 : IN std_logic;

Z : OUT std_logic

);

END COMPONENT;

--Inputs

signal A : std_logic := '0';

signal B : std_logic := '0';

signal C : std_logic := '0';

signal D : std_logic := '0';

signal S0 : std_logic := '0';

signal S1 : std_logic := '0';

--Outputs

signal Z : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: mux_4to1 PORT MAP (

A => A,

B => B,

C => C,

D => D,

S0 => S0,

S1 => S1,

Z => Z

);

-- Stimulus process

stim_proc: process

begin

-- hold reset state for 100 ns.

wait for 100 ns;  

A <= '1';

B <= '0';

C <= '1';

D <= '0';   

S0 <= '0'; S1 <= '0';

wait for 100 ns;  

S0 <= '1'; S1 <= '0';

wait for 100 ns;  

S0 <= '0'; S1 <= '1';

wait for 100 ns;   

S0 <= '0'; S1 <= '1';

wait for 100 ns;   

end process;

END;

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