[URGENT] Computer Architecture, Pipelining Question The Checked one, I don\'t kn

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[URGENT] Computer Architecture, Pipelining Question

The Checked one, I don't know why there is Stall(bubble)

Please someone help me

I really want to know this. please explain me.

4.14 This exercise is intended to help you understand the relationship between delay slots, control hazards, and branch execution in a pipelined processor. In this exercise, we assume that the following MIPS code is executed on a pipelined processor with a 5-stage pipeline, full forwarding, and a predict-taken branch ictor w r2.0(ri) label: beq r2.r0,1abe12 not taken once. then taken beq r3.r0.1abe 11 # taken add r1.r3.rl labe12: sw r1.0(r2) 4.14.1 [10j Draw the pipeline execution diagram for this code, assuming there are no delay slots and that branches execute in the EX stage. 4.14.5 [10] For the given code, what is the speedup achieved by moving branch execution into the ID stage? Explain your answer. In your speedup calculation, assume that the additional comparison in the ID stage does not affect clock cycle time

Explanation / Answer

The value of 0(R1) stored in R2 after the MEM state only. So, the next variable will assigned to R2 register after that.

Upto MEM state i.e. upto 4 clock cycles the R2 register will be busy. It is not possible to operate one register with 2 variables at a time. So the second instruction has to wait untli 5th clock cycle. After that second instruction will decode and the value in R2 will be overwritten.

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