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? 45 Lab#5-Logic Circuit in × | + (--) 0 ?? D file:///C/Users/a2zpr/AppDat/Local Packages/Microsoft.MicrosoftEdge 8 ekyb ds/Lab# 59620-962 OLogic%20Ci Lab #5-Logic Circuit in Xilinx ISE In Lab 3, we discovered that a Boolean expression describing the same logic behavior could be written in several different ways. We're going to implement the simplified Sum-of-Products (SOP) and Product-of-Sums (POS) expressions from Lab 3 using the Xilinx ISE (Integrated Synthesis Environment) Design Suite. Xilinx ISE is a software tool produced by Xilinx for synthesis and analysis of HDL designs, enabling the developer to synthesize ("compile") their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer [1]. Pre-Lab View the video found on the following website: Follow along with the tutorial on the EE2369 Wiki page named Give a 1-paragraph synopsis of the videos. https:/www.youtube.com/watch?v-FxFOM3DA68Y Xilinx ISE Getting Started and iMPACT Tutorial (pdf) Lab Similar to Lab 3, implement the following function using AND gates, OR gates and NOT gates using Xilinx ISE Schematic Capture. 2, F2(X, Y, Z) (X + Z)(X + Y) Assign X. Y. and Z to SW7, SW6, and SWS respectively, Fl should be assigned to LEDO, F2 to LEDI Verify, like Lab3, that F1 and F2 are indeed equal. The constraints file template is located in the Laboratory Wiki Page. It is named Spartan 3E DEFB User Constraints File Template Xilinx uses this file to link the output and inputs of your design to physical peripherals (switches, buttons, LEDs, etc.). 1047 PM 6/12/2018

Explanation / Answer

Solution: the Video describes the way of creating the scheatic of the logic circuits by using logic gates and how the gates are interconnected and the method of assigning pins to the input and outputs.

The following VHDL code is designed to implement the logic functions on the board by taking inputs afrom the dip switches SW1,SW2 and SW3 and the output is displayed on the LED1 and LED2.

VHDL Code:

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-- Company:

-- Engineer:

--

-- Create Date: 18:23:21 06/13/2018

-- Design Name:

-- Module Name: logigate - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity logigate is

Port ( SW7 : in STD_LOGIC; --X

SW6 : in STD_LOGIC; --Y

SW5 : in STD_LOGIC; --Z

LED0 : out STD_LOGIC;

LED1 : out STD_LOGIC);

end logigate;

architecture Behavioral of logigate is

begin

LED0 <= (SW7 and (not SW6)) or (SW5 and (not SW7));

LED1 <= (SW7 or SW5) and (not (SW7) or not(SW6));

end Behavioral;

User Constraints file

#Switches
NET "SW7" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW6" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW5" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
#LEDS
NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

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