? 5. (8 points) Given the following system R2 RI and R2 are two n-bit registers

Question

? 5. (8 points) Given the following system R2 RI and R2 are two n-bit registers For the adder-subtracter, addition is performed when select 1 and subtraction is performed when selectO cary(AB) The control inputs of register R1 (i.e.. load, sh?left, shift righ) are all active-high. load shift left shift right Ri ? For each of the following micro-operations in (a) to (f), answer parts i to ii by filling out the table directly on this page. (Note: Don't need to copy it to the blue book.) i) Which micro-operations are supported by the subsystem? If yes, complete parts ti and ii. If no, write "no" in part i and then leave parts ii and iti empty shift right, shift left) in order to support the micro-operation. micro-operations part i (yes part ii (put in "1" or "O for the ii) If a micro-operation is supported, indicate the values of the control inputs (i.e., select,load, ii) How many clock cycles are needed to complete the micro-operations part il (number of clock cycles or no) following control inputs) select - shift right shift right- select load select = shift left Ye load select - oad_ select# load = select = load shift left- shift right = shift left shift right shift left shift right = shift left = ; ; ; ;

Explanation / Answer

a. R1+R2 -> R1 - Yes - Select = 1; load = 1; shift left = 0; shift right =0; No. of clock cycle =1

b. R1-R2 -> R1 - Yes - Select = 0; load = 1; shift left = 0; shift right =0; No. of clock cycle =1

c. 0-> R1 - Yes - Select = 0; load = 0; shift left = 1; shift right =0; No. of clock cycle = n ( keep shifting to the left n times. Then the new bits that get stored in R1 will be zeros ).

d. R2' -> R1 - Yes - First make R1 =0 as indicated in c. then Select = 0; load = 1; shift left = 0; shift right =0; No. of clock cycle =1. Since select = 0, output of adder / subtractor = A-B = 0-R2 = R2'

e. R2'+1 -> R1; No - since : Obtain R2' as shown in d. Now, A= R2' and B = R2. If Select = 1, then output of adder / subtractor = A+B = R2 + R2' = 1, Now load =1; shift left = 0; shift right = 0 and clock cycle =1 => R1= 1 , we can get 1, but R2' is lost.

f. R1*2 -> R1 Yes - Select = 0; load = 0; shift left = 1; shift right =0; No. of clock cycle =? 1 ( One left shift will multiply the value by 2 and the new no. is still in R1 )

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