Academic Integrity: tutoring, explanations, and feedback — we don’t complete graded work or submit on a student’s behalf.

\"main\" method (pseudo code) [ .codel For each of the following commands, first

ID: 2292773 • Letter: #

Question

"main" method (pseudo code) [ .codel For each of the following commands, first execute ie command in hex and print the command an the result. Then execute it again in binary and print it. SHL, SHR, SAL, SAR (binary only) ROL, ROR, RCL, RCR (binary only) SHLD, SHRD (hex only) Note: Give the register an initial value of 10001101. The count you shift/rotate should be 2. Each time you execute another command, reset the value of the register. You can play around with other values, but what you submit to me in the lab should execute these values or I will not grade it.

Explanation / Answer

Since the architecture isn't mentioned, I assume INTEL 8085 processor environment. Suppose that the source register is B containing 10001101{8D H} and destination register [where the value after operation is stored] is C.

MVI B,8DH; // or you may use this: MVI %b,$008D;

SHLD C,B,02H; // or you may use this: SHLD %c,%b,$2;

This instruction left-shifts the values stored in reg B by count value of 2 and stores result in reg C. The two right most bits are filled by most significant bits of source register.

MVI B,8DH; // H stands for hexadecimal

SHRD C,B,02H;

This instruction right-shifts the values stored in reg B by count value of 2 and stores result in reg C. The two left most bits are filled by least significant bits of source register.

Originally, both SHLD & SHRD are meant for 16 and 32 bit registers.

MVI B,10001101b; // or you may use this: MVI %b,$8D

SHL B,02H; // or you may use this: SHL%b,$2

MVI B,10001101b;

SHR B,02H;

This instruction logically shifts source register contents either right or left.

MVI B,10001101b; //or you may use this: MVI %b,$8D

SAL B,02H; //or you may use this: SAL%b,$2

MVI B,10001101b;

SAR B,02H;

Both SAL and SAR shifts arithmatically to left and right respectively the contents of reg B.

MVI B,10001101b;

ROL B,02H;

MVI B,10001101b;

ROR B,02H;

MVI B,10001101b;

RCL B,02H;

MVI B,10001101b;

RCR B,02H;

Note that you may use $02 in place of 02H and %b in place of B in the above codes, depending on architecture of processor.

Any doubts, please ask. Thumbs down won't solve your doubt.

Thanks!