Suppose your colleague, a systems engineer, provides you with a code and schemat

Question

Suppose your colleague, a systems engineer, provides you with a code and schematic for a 4-bit shift register. She would like a D flip-flop with a 2-to-1 multiplexer as part as her design, and would like to call this component muxdff, but is unsure on how to create the muxdff component herself. She has envisioned that the 2-to-1 multiplexer can select two different states of a D flip-flop. As shown below, she wants to have four D flip-flops total. Do keep in mind that her schematic may not be fully complete, and that it may be a top-level/block-level drawing only. Help out your colleague, and generate the complete code for muxdff to help her complete her design. LIBRARY ieee; USE ieee.std.logic.1164.all; ENTITY shift4 IS PORT (R STD.LOGIC.VECTOR(3 DOWNTO O) STD LOGIC; L, w, Clock : IN :BUFFER STDLOGIC.VECTOR(3 DOWNTO 0)); END shift4 ARCHITECTURE Structure OF shift4 IS COMPONENT muxdf PORT ( DO, DI, Sel, Clock :IN STD LOGIC :OUT STD LOGIC) Qu END COMPONENT BEGIN Stage3: muxdf PORT MAP (w, R(3), L, Clock, Q(3)); Stage2: muxdf PORT MAP (Q(3), R(2), L, Clock, Q(2)); Stage1: muxdf PORT MAP ( Q(2), R(1), L, Clock, Q(1)) Stage0: muxdfi PORT MAP (Q(1), R(0), L, Clock, Q(0)) END Structure ; Clock

Explanation / Answer

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY shift4 IS
   PORT (
           R :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
           L,w,Clock :IN STD_LOGIC;
           Q :BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));
END shift4;
ARCHITECTURE Strucure OF shift4 IS
COMPONENT muxdf
   PORT(D0,D1,sel,Clock : IN STD_LOGIC;
       Q : OUT STD_LOGIC);  
   PROCESS (clock)
       Q<= D1 when (sel = '1') else D0;
       BEGIN      
       IF (clock'EVENT AND clock = '1') THEN
           CASE mode IS
               WHEN 0 => Q := Q;
               WHEN 1 => Q(2 DOWNTO 0) := Q(3 DOWNTO 1);
                      Q(3) := w;
               WHEN 2 => Q(3 DOWNTO 1) := Q(2 DOWNTO 0);
                         Q(0) := w;
               WHEN 3 => Q := R;
           END CASE;
       END IF;
   END PROCESS;
END COMPONENT;
BEGIN  
   Stage3: muxdff PORT MAP(w,R(3),L,Clock,Q(3));
   Stage2: muxdff PORT MAP(Q(3),R(2),L,Clock,Q(2));
   Stage1: muxdff PORT MAP(Q(2),R(1),L,Clock,Q(1));
   Stage0: muxdff PORT MAP(Q(1),R(0),L,Clock,Q(0));
END Structure;

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