Using only VERILOG coding, create a two-digit BCD adder. This circuit will add u
ID: 2291321 • Letter: U
Question
Using only VERILOG coding, create a two-digit BCD adder. This circuit will add up the points earned each round to the total. Stored the total points earned in an 8-bit register. The outputs will be routed to 7-segment displays DIS2..DIS1. 9 points for an exact guess, 4 points for a “low” guess, and zero points for a “high” guess. Pushbutton switch S2 will reset the point total to 00. The maximum point total possible is 81, based on making exact guesses on each of the 9 rounds. Verify that the point total display updates on each round as expected and “freezes” once round 9 is completed.
Explanation / Answer
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity bcdcounter1 is
port (
RST : in std_logic;
Digit1_O : out unsigned(3 downto 0);
Digit2_O : out unsigned(3 downto 0);
CLK : in std_logic
);
end bcdcounter1;
architecture bcdcounter1_arch of bcdcounter1 is
signal Digit1 : unsigned(3 downto 0);
signal Digit2 : unsigned(3 downto 0);
begin
process (CLK,RST)
begin
if RST = '0' then
Digit1 <= (others=>'0');
elsif rising_edge(CLK) then
if Digit1 > 0 then
Digit1 <= Digit1 - 1;
else
Digit1 <= (others=>'0');
end if;
end if;
if RST = '0' then
Digit2 <= (others=>'0');
elsif rising_edge(CLK) then
if Digit2 > 0 then
Digit2 <= Digit1 - 1;
else
Digit1 <= (others=>'0');
end if;
end if;
end process;
Digit1_O <= Digit1;
end bcdcounter1_arch
another method
-- Description of a two digit BCD counter
--
-- ports :
--
-- Clk : Clock signal
-- Clear : Asynchronous active low clear signal
-- Load : Synchronous active high load signal
-- Enable : Synchronous active high count enable signal
-- DataIn : 8 bit input port for preset of counter
-- 7 downto 4 for most significant digit
-- 3 downto 0 for least significant digit
-- DataOut : 8 bit output port for BCD counter
-- 7 downto 4 for most significant digit
-- 3 downto 0 for least significant digit
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bcd is
port(
Clk : in std_logic;
Clear : in std_logic;
Load : in std_logic;
Enable : in std_logic;
DataIn : in std_logic_vector(7 downto 0);
DataOut : out std_logic_vector(7 downto 0)
end bcd;
architecture RTL of bcd
-- signal declaration
signal CountL : std_logic_vector(3 downto 0);
signal CountL : std_logic_vector(3 downto 0);
signal next_CountH : std_logic_vector(3 downto 0);
signal next_CountH : std_logic_vector(3 downto 0);
signal CountL_TC : std_logic;
begin
procCountL: process(Clk,Clear)
begin
if (Clear = '0')then
CountL <= (others => '0');
elsif(Clk'event and Clk = '1')then
if (Load = '1')then
if (DataIn(3 downto 0) > "1001")then
CountL <= "1001";
else
CountL <= DataIn(3 downto 0);
end if;
elsif(Enable = '1')then
if (CountL = "1001")then
CountL <= (others => '0');
else
CountL <= CountL + 1;
end if;
end if;
end if;
end process procCountL;
CountL_TC <= '1' when CountL = "1001" else '0';
procCountH: process(Clk,Clear)
begin
if (Clear = '0')then
CountH <= (others => '0');
elsif(Clk'event and Clk = '1')then
if (Load = '1')then
if (DataIn(7 downto 4) > "1001")then
CountH <= "1001";
else
CountH <= DataIn(7 downto 4);
end if;
elsif(Enable = '1' and CountL_TC = '1')then
if (CountH = "1001")then
CountH <= (others => '0');
else
CountH <= CountH + 1;
end if;
end if;
end if;
end process procCountH;
DataOut <= CountH & CountL;
end RTL;
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