Hello, I am having trouble compiling the following code, I keep getting errors i
ID: 2291134 • Letter: H
Question
Hello,
I am having trouble compiling the following code, I keep getting errors in temp_h0, temp_h1, temp_m1, temp_m0. Below are the top modules and submodules. Thank you for your time!
Submodule
module clock(input clk_in, input [31:0] clkscale, output reg clk_out);
// output clk_out frequency = input cclk_in frequency / (2* clkscale)
reg [31:0] clkQ = 0; // 2^32-1>25M
always @(posedge clk_in)
begin
clkQ = clkQ + 1; // add 1, every cycle of clk_in
if (clkQ == clkscale)
begin // toggle every clckscale cycles
clk_out = ~clk_out;
clkQ = 0;
end
end
endmodule
module BCD2LEDS(bcd,leds);
input[3:0]bcd;
output reg [6:0]leds;
always @ (*)
case (bcd) //7'b6543210;
4'b0000: leds = 7'b1000000; //0
4'b0001: leds = 7'b1111001; //1
4'b0010: leds = 7'b0100100; //2
4'b0011: leds = 7'b0110000; //3
4'b0100: leds = 7'b0011001; //4
4'b0101: leds = 7'b0010010; //5
4'b0110: leds = 7'b0000010; //6
4'b0111: leds = 7'b1111000; //7
4'b1000: leds = 7'b0000000; //8
4'b1001: leds = 7'b0011000; //9
default: leds = 7'b1111111; //off
endcase
endmodule
Top Module
module Lab4Part1 ( CLOCK_50, SW,
HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7);
input CLOCK_50; // 50MHz clock
input [17:0] SW;
// SW[17]=1 time setting mode
// 0 clock running mode
//When SW[17]=1, SW[15:12] for hour1, SW[11:8] for hour0, setting 2-digit hr
// When SW[17]=1, SW[7:4] for minute1, SW[3:0] for minute0, setting 2-digit min
// second1, second0 are 00, setting 2-digit sec
output [0:6] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
// HEX5 HEX4 for hour
// HEX3 HEX2 for minute
// HEX1 HEX0 for second
reg [3:0] hex_h1, hex_h0, _m1, temp_m0, temp_s1, temp_s0;
// clock(input clk_in, input [31:0] clkscale, output reg clk_out);
clock M0 (CLOCK_50, 25000000, clock_1Hz); // clock1Hz
// generate 1Hz clock
BCD2LEDS hour1 (temp_h1, HEX5); // BCD2LEDS
BCD2LEDS hour0(temp_h0, HEX4);
BCD2LEDS minute1(temp_m1, HEX3);
BCD2LEDS minute0(temp_m0, HEX2);
BCD2LEDS second1(temp_s1, HEX1);
BCD2LEDS second0(temp_s0, HEX0);
assign HEX6=7'b1111111;
assign HEX7=7'b1111111;
always @ (posedge clock_1Hz)
begin
if(SW[17])
begin
temp_h1=SW[15:12];
temp_h0=SW[11:8];
temp_m1=SW[7:4];
temp_m0=SW[3:0];
end
else
begin
temp_s0=temp_s0+1;
if (temp_s0 == 10)
begin
temp_s0 = 0;
temp_s1 = temp_s1+1;
if (temp_s1 == 6)
begin
temp_s1 = 0;
temp_m0 =temp_m0+1;
if (temp_m0 ==10)
begin
temp_m0 = 0;
temp_m1 = temp_m1+1;
if(temp_m1 == 6)
begin
temp_m1 = 0;
temp_h0 = temp_h0+1;
if((temp_h1 <= 1) && (temp_h0 == 10))
begin
temp_h0 =0;
temp_h1 = temp_h1+1;
end
else if (temp_h1==2 && temp_h0==4)
begin
temp_h0 =0;
temp_h1 =0;
end
end
end
end
end
end
end
endmodule
Circuit Block Diagram and Description sw3-0] SW15-12) S11-8 SW[17] preset h1 ho m1 mo 50MHz 1Hz counter (mod-60) fregdivider hour min sec 7-seg 7-seg 7-seg 7-seg 7-seg 7-seg Fig.1 the diagram of digital cloc!k The digital clock can display the hours (00 to 23), minutes (00 to 59) and seconds (00 to 59) at the same time using six (6) 7-segment displays. The initial time can be preset by switches as follows: when SW[17]-1 (time setting mode), SW[15-0] will preset a 4-digit BCD number for initial hours and minutes, initial second is always 00; when SW[17]-0 (clock running mode), the digital clock will work normally starting with the preset hours and minutes and 0 second.Explanation / Answer
In top module declare temp_h0, temp_h1, temp_m0, temp_m1 as registers as in procedural assignment left hand side should be register.
input CLOCK_50; // 50MHz clock
input [17:0] SW;
// SW[17]=1 time setting mode
// 0 clock running mode
//When SW[17]=1, SW[15:12] for hour1, SW[11:8] for hour0, setting 2-digit hr
// When SW[17]=1, SW[7:4] for minute1, SW[3:0] for minute0, setting 2-digit min
// second1, second0 are 00, setting 2-digit sec
output [0:6] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
// HEX5 HEX4 for hour
// HEX3 HEX2 for minute
// HEX1 HEX0 for second
reg [3:0] hex_h1, hex_h0, temp_s1, temp_s0;
reg temp_h0, temp_h1, temp_m0, temp_m1; // Declare as registers
// clock(input clk_in, input [31:0] clkscale, output reg clk_out);
clock M0 (CLOCK_50, 25000000, clock_1Hz); // clock1Hz
// generate 1Hz clock
BCD2LEDS hour1 (temp_h1, HEX5); // BCD2LEDS
BCD2LEDS hour0(temp_h0, HEX4);
BCD2LEDS minute1(temp_m1, HEX3);
BCD2LEDS minute0(temp_m0, HEX2);
BCD2LEDS second1(temp_s1, HEX1);
BCD2LEDS second0(temp_s0, HEX0);
assign HEX6=7'b1111111;
assign HEX7=7'b1111111;
always @ (posedge clock_1Hz)
begin
if(SW[17])
begin
temp_h1=SW[15:12];
temp_h0=SW[11:8];
temp_m1=SW[7:4];
temp_m0=SW[3:0];
end
else
begin
temp_s0=temp_s0+1;
if (temp_s0 == 10)
begin
temp_s0 = 0;
temp_s1 = temp_s1+1;
if (temp_s1 == 6)
begin
temp_s1 = 0;
temp_m0 =temp_m0+1;
if (temp_m0 ==10)
begin
temp_m0 = 0;
temp_m1 = temp_m1+1;
if(temp_m1 == 6)
begin
temp_m1 = 0;
temp_h0 = temp_h0+1;
if((temp_h1 <= 1) && (temp_h0 == 10))
begin
temp_h0 =0;
temp_h1 = temp_h1+1;
end
else if (temp_h1==2 && temp_h0==4)
begin
temp_h0 =0;
temp_h1 =0;
end
end
end
end
end
end
end
endmodule
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