1. Using a case statement, write a Verilog HDL behavioral description of an eigh

Question

1. Using a case statement, write a Verilog HDL behavioral description of an eight-bit arithmetic- logic unit (ALU). The circuit has a three-bit select bus (Sel), eight-bit input datapaths (Al7:0] and B[7:0]), and eight-bit output datapath (vl7:0]), and performs the arithmetic and logic operations listed below Sel Operation YEA& B | y-A l B Description Clear Bitwise AND e 001 010 | Bitwise OR o 011 y A A BBitwise exclusive OR 100 101 YA Bitwise complement Subtract 110 Y A+BAdd - 8'hFF Set Given the following circuit: (1) Using Verilog gate-level primitives, develop a structural model; (2) Using continuous assignments, develop a behavioral model; (3) Write a test bench for either model.

Explanation / Answer

Answer to part a)

Part 2)

1. Structural model

2. Continuous Assignment

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