Write a VHDL code for the register module which has the following features: Para
ID: 2268273 • Letter: W
Question
Write a VHDL code for the register module which has the following features:
Parameters:
- the size of the word to store, in bits. To be called n.
- the value to which the register will reset to. To be called r.
Inputs:
- in (n-1 bits) : parallel input to be stored.
- clk: clock signal. the register file is rising edge triggered.
- we: write enable allows register contents to be written
- rst: resets the register to r. Asynchronous
Outputs:
- out (n-1 bits): parallel output of the register module
Consider using the behavioral style for the register module.
clk Register ModuleExplanation / Answer
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity register_nbit is
generic (
n : integer := 4;
r : integer := 0
);
port (
clk : in std_logic;
rst : in std_logic;
wen : in std_logic;
in1 : in std_logic_vector(n-1 downto 0);
out1 : out std_logic_vector(n-1 downto 0)
);
end register_nbit;
architecture behave of register_nbit is
begin
process(clk)
begin
if(clk'event and clk = '1') then
if (rst = '1') then
out1 <= std_logic_vector(to_unsigned(r, out1'length));
elsif (wen = '1') then
out1 <= in1;
end if;
end if;
end process;
end behave;
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