Modify your Verilog file ( file at the end of this page) to include additional d

Question

Modify your Verilog file ( file at the end of this page) to include additional display of the output f to 7 - segment display HEX0. Your Verilog module should have 2 inputs x1 and x2, the output f and the 7 - bit output HEX0. HEX0 can be declared as:

output reg [6:0] HEX0; If output f is 1 , HEX0 displays 1; otherwise HEX0 displays 0. For 7 - segment display, a pplying a low logic level (Logic 0) to a segment wi ll light it up, and applying a high logic level turns it off. For example, if HEX0 is 7’b1000000, then the 7 - segment will display 0. Us e cyclic behavior (always) to describe the required logic for the display.

module light (x1, x2, f);

input x1, x2;

output f;

assign f=(x1&~x2)|(~x1&x2);

endmodule

Explanation / Answer

module light (x1, x2, f, HEX0); input x1, x2; output f; output reg [6:0] HEX0; assign f = (x1 & ~x2) | (~x1 & x2); always @(*)   begin    if (f == 1'b1)    HEX0 = 7'b1001111;    else    HEX0 = 7'b1000000;   end endmodule

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