--debouncer_red_tb provided library ieee; use ieee.std_logic_1164.all; use ieee.
ID: 2268063 • Letter: #
Question
--debouncer_red_tb provided
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity debounce_red_tb is
end debounce_red_tb;
architecture rtl of debounce_red_tb is
-- Inputs to design under test
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal input : std_logic;
-- Actual outputs
signal debounce_out : std_logic;
signal red_out : std_logic;
constant T : time := 10 ns ;
constant rw : time := 100 ns ;
constant ps : time := 400 ns ;
constant pw : time := 50 ns ;
constant iw : time := 1000 ns ;
constant npb : integer := 4;
constant npa : integer := 5;
begin
-- Instantiate the Unit Under Test (UUT)
lab1_cct2_design : entity work.debounce_red port map(
clk => clk,
rst => rst,
input => input,
debounce_out => debounce_out,
red_out => red_out
);
clk <= not clk after T/2; -- generate clock
-- generate reset signal
rst_gen: process
begin
rst <= '1';
wait for rw;
rst <= '0';
wait;
end process;
-- Provide inputs
input_stim: process
begin
input <= '0';
wait for ps;
for i in 1 to npb loop
input <= '1';
wait for pw;
input <= '0';
wait for pw;
end loop;
input <= '1';
wait for iw;
for i in 1 to npa loop
input <= '0';
wait for pw;
input <= '1';
wait for pw;
end loop;
input <= '0';
wait;
end process;
end rtl;
Task 2: Debouncer & Rising Edge Detector (RED) Develop VHDL RTL description of the DEBOUNCE RED unit, based on the interface shown in Fig. 3 and the internal block diagrams shown in Figs. 4, 5, and 6 Your description should use two levels of hierarchy as shown in Fig. 4. clk rst debounceout - input DEBOUNCE_RED red out Fig. 3: Interface of DEBOUNCE_RED. debounce out rst clk -|reset DE BOUNCER output input debounce_out rsRED output^ red out Fig. 4: Block diagram of DEBOUNCE REDExplanation / Answer
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity debounce_red_tb is
end debounce_red_tb;
architecture rtl of debounce_red_tb is
-- Inputs to design under test
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal input : std_logic;
-- Actual outputs
signal debounce_out : std_logic;
signal red_out : std_logic;
constant T : time := 10 ns ;
constant rw : time := 100 ns ;
constant ps : time := 400 ns ;
constant pw : time := 50 ns ;
constant iw : time := 1000 ns ;
constant npb : integer := 4;
constant npa : integer := 5;
begin
-- Instantiate the Unit Under Test (UUT)
lab1_cct2_design : entity work.debounce_red port map(
clk => clk,
rst => rst,
input => input,
debounce_out => debounce_out,
red_out => red_out
);
clk <= not clk after T/2; -- generate clock
-- generate reset signal
rst_gen: process
begin
rst <= '1';
wait for rw;
rst <= '0';
wait;
end process;
-- Provide inputs
input_stim: process
begin
input <= '0';
wait for ps;
for i in 1 to npb loop
input <= '1';
wait for pw;
input <= '0';
wait for pw;
end loop;
input <= '1';
wait for iw;
for i in 1 to npa loop
input <= '0';
wait for pw;
input <= '1';
wait for pw;
end loop;
input <= '0';
wait;
end process;
end rtl;
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