Write a VHDL or verilog program for an 8 bit LFSR structure which generates all

ID: 2267910 • Letter: W

Question

Write a VHDL or verilog program for an 8 bit LFSR structure which generates all values in a range from 1 to 255 in a pseudo random way. To avoid the LFSR being stalled at 0, the initial state can be set at any value other than 0. Smaller ranges of values can be extracted from the main 8-bit register. The bit 0 can be used as a sign bit to generate positive and negative numbers.

the data is already split into a sequence of 2 bit symbols

The system has a control pin to inject or not inject noise

the user can set the level of noise, when injected, in one of the following ranges(-8,7),(-16,15),(-32,31),(-64,63).

Explanation / Answer

LFSR source code.

module LFSR8_11D(
input clk,
output reg [7:0] LFSR = 255 // put here the initial value
);

wire feedback = LFSR[7];

always @(posedge clk)
begin
LFSR[0] <= feedback;
LFSR[1] <= LFSR[0];
LFSR[2] <= LFSR[1] ^ feedback;
LFSR[3] <= LFSR[2] ^ feedback;
LFSR[4] <= LFSR[3] ^ feedback;
LFSR[5] <= LFSR[4];
LFSR[6] <= LFSR[5];
LFSR[7] <= LFSR[6];
end
endmodule

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Write a VHDL or verilog program for an 8 bit LFSR structure which generates all

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