Design a data sorting (ascending order) circuit in verilog. Given the Alphabet =

Question

Design a data sorting (ascending order) circuit in verilog. Given the Alphabet ={0,1,2,3,4,5,6,7,8,9} you have to design a circuit for sorting frequencies of occurrence of symbols already calculated and stored in the SRAM memory-buffer. Write a memory buffer, with memory of width=8 (max number=255) and the Depth=10 (number of symbols in the Alphabet). Initialize the memory with frequencies for a sequence of length 255.    initial $readmemh ("txtfile.dat", memory);
txtfile.dat is a memory map txt file with each line containing frequencies of occurrence in a hypothetic sequence hex. Assume that all symbols occur, that is there is no null frequencies. The frequencies are placed in lexicographical order of symbols, that is FB[0] =N 0 , FB[1] =N 1 etc. Where N(i) - are frequencies. The Sum of all frequencies is not to exceed 255. The Sample contents in txtfile.dat : 0e 10 03 20 11 3c 4D 15 16 01 Write a testbench to test output data. Data are to be ordered as follows: 01, 03,10, 11, 15, 16,…,4D
Design a data sorting (ascending order) circuit in verilog. Given the Alphabet ={0,1,2,3,4,5,6,7,8,9} you have to design a circuit for sorting frequencies of occurrence of symbols already calculated and stored in the SRAM memory-buffer. Write a memory buffer, with memory of width=8 (max number=255) and the Depth=10 (number of symbols in the Alphabet). Initialize the memory with frequencies for a sequence of length 255.    initial $readmemh ("txtfile.dat", memory);
txtfile.dat is a memory map txt file with each line containing frequencies of occurrence in a hypothetic sequence hex. Assume that all symbols occur, that is there is no null frequencies. The frequencies are placed in lexicographical order of symbols, that is FB[0] =N 0 , FB[1] =N 1 etc. Where N(i) - are frequencies. The Sum of all frequencies is not to exceed 255. The Sample contents in txtfile.dat : 0e 10 03 20 11 3c 4D 15 16 01 Write a testbench to test output data. Data are to be ordered as follows: 01, 03,10, 11, 15, 16,…,4D
Design a data sorting (ascending order) circuit in verilog. Given the Alphabet ={0,1,2,3,4,5,6,7,8,9} you have to design a circuit for sorting frequencies of occurrence of symbols already calculated and stored in the SRAM memory-buffer. Write a memory buffer, with memory of width=8 (max number=255) and the Depth=10 (number of symbols in the Alphabet). Initialize the memory with frequencies for a sequence of length 255.    initial $readmemh ("txtfile.dat", memory);
txtfile.dat is a memory map txt file with each line containing frequencies of occurrence in a hypothetic sequence hex. Assume that all symbols occur, that is there is no null frequencies. The frequencies are placed in lexicographical order of symbols, that is FB[0] =N 0 , FB[1] =N 1 etc. Where N(i) - are frequencies. The Sum of all frequencies is not to exceed 255. The Sample contents in txtfile.dat : 0e 10 03 20 11 3c 4D 15 16 01 Write a testbench to test output data. Data are to be ordered as follows: 01, 03,10, 11, 15, 16,…,4D

Explanation / Answer

Verilog code for Ascending order
> //Bubble sort Version
>
> module priority_queue (clk,reset,d_en,d_in, d_out);
>
> parameter n = 10; //Number of inputs
> parameter s = 32; //Size of the register
>
> input clk;
> input reset;
> input [s-1:0] d_in;
> input d_en;
> output [s-1:0] d_out;
>
> reg [s-1:0] d_out;
>
> reg [s-1:0] reg_in [n-1 :0]; //Input registers
> reg [s-1:0] reg_out [n-1:0]; // Output registers
>
> reg [5:0] addr_in; //Input register data pointer
> reg [5:0] addr_out; // Output register data pointer
>
> reg d_sort;
>
> reg [5:0]sort_count;
>
> integer i,j;
>
> always @ (posedge clk)
> begin
> if(reset)
> begin
> for(i=0; i<n; i=i+1)
> reg_out [i] <= 32'd0;
> addr_in <=6'd0;
> addr_out <=6'd0;
> d_out<= 32'd0;
> d_sort<=1'b0;
> sort_count <=6'd0;
> end
>
> else if (d_en)
> begin
> reg_in[addr_in] <= d_in;
> addr_in <= addr_in +1'b1;
> addr_out <= 6'd0;
> end
>
> else if (!d_en)
> begin
> for (j=n-1; j>=1; j=j-1)
> begin
> for (i=0; i<= n-2; i=i+1)
> begin
> if(reg_in[i] > reg_in[i+1]) //Comparison
> operation
> begin
> reg_in[i] <= reg_in[i+1]; // Swapping
> reg_in[i+1]<= reg_in[i]; // swapping
> end
> reg_out[i] <= reg_in[i]; //Transfering input
> reg value to output registers.
> end
> sort_count <= sort_count +1'b1;
> end
> if( sort_count == (n-1))
> d_sort <=1'b1;
> end
>
> if(d_sort)
> begin
> d_out<= reg_out[addr_out];
> addr_out <= addr_out + 1'b1;
> addr_in <= 6'd0;
>
> end
>
> end
> endmodule

Venkatesh wrote in post #4626178:
> //Bubble sort Version 1 - 06/17/2016
>
> module priority_queue (clk,reset,d_en,d_in, d_out);
>
> parameter n = 10; //Number of inputs
> parameter s = 32; //Size of the register
>
> input clk;
> input reset;
> input [s-1:0] d_in;
> input d_en;
> output [s-1:0] d_out;
>
> reg [s-1:0] d_out;
>
> reg [s-1:0] reg_in [n-1 :0]; //Input registers
> reg [s-1:0] reg_out [n-1:0]; // Output registers
>
> reg [5:0] addr_in; //Input register data pointer
> reg [5:0] addr_out; // Output register data pointer
>
> reg d_sort;
>
> reg [5:0]sort_count;
>
> integer i,j;
>
> always @ (posedge clk)
> begin
> if(reset)
> begin
> for(i=0; i<n; i=i+1)
> reg_out [i] <= 32'd0;
> addr_in <=6'd0;
> addr_out <=6'd0;
> d_out<= 32'd0;
> d_sort<=1'b0;
> sort_count <=6'd0;
> end
>
> else if (d_en)
> begin
> reg_in[addr_in] <= d_in;
> addr_in <= addr_in +1'b1;
> addr_out <= 6'd0;
> end
>
> else if (!d_en)
> begin
> for (j=n-1; j>=1; j=j-1)
> begin
> for (i=0; i<= n-2; i=i+1)
> begin
> if(reg_in[i] > reg_in[i+1]) //Comparison
> operation
> begin
> reg_in[i] <= reg_in[i+1]; // Swapping
> reg_in[i+1]<= reg_in[i]; // swapping
> end
> reg_out[i] <= reg_in[i]; //Transfering input
> reg value to output registers.
> end
> sort_count <= sort_count +1'b1;
> end
> if( sort_count == (n-1))
> d_sort <=1'b1;
> end
>
> if(d_sort)
> begin
> d_out<= reg_out[addr_out];
> addr_out <= addr_out + 1'b1;
> addr_in <= 6'd0;
>
> end
>
> end
> endmodule}
> reg [s-1:0] d_out;
>
> reg [s-1:0] reg_in [n-1 :0]; //Input registers
> reg [s-1:0] reg_out [n-1:0]; // Output registers
>
> reg [5:0] addr_in; //Input register data pointer
> reg [5:0] addr_out; // Output register data pointer
>
> reg d_sort;
>
> reg [5:0]sort_count;
>
> integer i,j;
>
> always @ (posedge clk)
> begin
> if(reset)
> begin
> for(i=0; i<n; i=i+1)
> reg_out [i] <= 32'd0;
> addr_in <=6'd0;
> addr_out <=6'd0;
> d_out<= 32'd0;
> d_sort<=1'b0;
> sort_count <=6'd0;
> end
>
> else if (d_en)
> begin
> reg_in[addr_in] <= d_in;
> addr_in <= addr_in +1'b1;
> addr_out <= 6'd0;
> end
>
> else if (!d_en)
> begin
> for (j=n-1; j>=1; j=j-1)
> begin
> for (i=0; i<= n-2; i=i+1)
> begin
> if(reg_in[i] > reg_in[i+1]) //Comparison
> operation
> begin
> reg_in[i] <= reg_in[i+1]; // Swapping
> reg_in[i+1]<= reg_in[i]; // swapping
> end
> reg_out[i] <= reg_in[i]; //Transfering input
> reg value to output registers.
> end
> sort_count <= sort_count +1'b1;
> end
> if( sort_count == (n-1))
> d_sort <=1'b1;
> end
>
> if(d_sort)
> begin
> d_out<= reg_out[addr_out];
> addr_out <= addr_out + 1'b1;
> addr_in <= 6'd0;
>
> end
>
> end
> endmodule

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