WRITE VHDL CODE FOR TASK Consider the design of a sequential circuit that could
ID: 2266918 • Letter: W
Question
WRITE VHDL CODE FOR TASK
Consider the design of a sequential circuit that could control a vending machine. Suppose that a coin-operated vending machine dispenses accepts nickels and dimes. All electronic signals in the vending machine are synchronized to the positive edge of a clock signal, named Clock. The vending machine's coin-receptor mechanism generates two signals, sensep and senseN, which are asserted when a dime or a nickel is detected. Because the coin receptor is a mechanical device and thus very slow compared to an electronic circuit, inserting a coin causes senseo or senseN to be set to 1 for a large number of clock cycles. We wil assume that the coin receptor also generates two other signals, named Dand N. The D signal is set to 1 for one clock cycle after sense D becomes 1, and N is set to 1 for one clock cycle after sense N becomes 1. The timing relationships between Clock, senseo and senseN, D, and N areillustrated in timing diagram bellow. The hash marks on the waveforms indicate that sense D or sense N may be 1 for many clock cycles. Also, there may be an arbitrarily long time between the insertion of two consecutive coins. Note that since the coin receptor can accept only one coin at a time, it is not possible to have both D and N set to 1 at once. Clock senses sense Figure 1: Tming Diagranm Figure 2 shows circuit that generates N, and Figure 3 provides state diagram for described operation. Write VHDL code for the FSM shown in Figure 3, using the style of code implemented in Lab set 4 part 2. sensen D O D O Clock Figure 2: Circuit that generated N DN S1/0 83/0 0 DN DN 52/0 S4/1 Figure 3: FSM state diagramExplanation / Answer
library ieee;
use ieee.std_logic_1164.all;
entity Dl is
port(d:in bit; q,qbar:buffer bit);
end Dl;
architecture virat of Dl is
signal s1,r1:bit;
begin
q<= d nand qbar;
qbar<= d nand q;
end virat;
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