Where can I find the solution in the online book for this page ? I\'m kind of lo

Question

Where can I find the solution in the online book for this page ? I'm kind of lost

160LOGIC GATES 3. The output of an AND gate with inputs A, B, and C is a 1 (HIGH) when (a) A = 1,B=1,C-1 (b) A-1,B=0,Cm] (c) A=0,B-0, C-0 4. The output of an OR gate with inputs A, B, and Cis a 1 (HIGH) whern (a) A-1, B-1, C = I (d) answers (a), (b), and (c) (b) A = 0, B = 0, C-1 (c) A 0, B-0, C = 0 (e) only answers (a) and (b) 5, A pulse is applied to each input of a 2-input NAND gate. One pulse goes HIGH at 0 and goes back Low at 1 ms. The other pulse goes HIGH at 1-3 ms. The output pulse can be described as follows: (a) lt goes LOW at 0 and back HIGH at , = 3 ms. (b) It goes Low at 0.8 ms and back HIGH at 3 ms. (c) It goes Low at 0.8 ms and back HIGH at 1 ms. (d) It goes LOW at 0.8 ms and back LOW at Ims. 0.8 ms and goes back Low at 6. A pulse is applied to each input of a 2-input NOR gate. One pulse goes HIGH at0 and goes back LOW at 1-1 ms. The other pulse goes HIGH at 0.8 ms and goes back Low at 3 ms. The output pulse can be described as follows: (a) It goes LOW at-0 and back HIGH at3 ms. (b) It goes Low at , 0.8 ms and back HIGH at 1-3 ms. (c) It goes LOW at 0.8 ms and back HIGH at 1-1 ms. (d) It goes HIGH at , = 0.8 ms and back LOW at 1-1 ms 7. A pulse is applied lo each input of an exclusive-OR gate. One pulse goes HIGH at 0 and goes back Low at 1-1 ms. The other pulse goes HIGH at , 0.8 ms and goes back LOW at 3 ms. The output pulse can be described as follows: (a) It goes HIGH at 1-0 and back Low at 3 ms. (b) It goes HIGH at 1 = 0 and back Low at 0.8 ms. (c) It goes HIGH at 1 ms and back LOW at-3 ms. (d) both answers (b) and (c)

Explanation / Answer

Answer:-3) The output of an AND gate is HIGH(1) only when all the inputs are HIGH. So option (a) is correct, i.e when all A=1, B=1, and C=1.

Answer:-4) The output of a OR gate is HIGH only when any one of the input is HIGH i.e in this case either of the input HIGH will cause output to be HIGH. So here option (e) is correct i.e both a and b will make output HIGH.

Answer:-5) NAND gate is opposite of AND gate. For NAND if all inputs are HIGH then only output is LOW otherwise output wil be HIGH.

Here both the inputs are high from t=0.8 ms to t=1 ms. In this time frame the output will be LOW. In other time frame output will be HIGH. So option (c) is correct.

Answer:-6) NOR gate is just opposite of OR gate. NOR gate outpit is HIGH only when all the inputs to NOR are LOW. In other case NOR output is always LOW.

Here both inputs are never at LOW state at the same time, at any time we see any one of the input is at HIGH state. So in this case output will be always LOW. Hence option (a) is correct.

Answer:-7) EX-OR gate output is HIGH only when odd number of inputs are HIGH else output is low.

Here we have two inputs, one input is HIGH and other is LOW for 0 < t < 0.8 ms, so output will be HIGH in this time.

From 0.8 < t < 1 ms, both are HIGH so output will be LOW.

From 1 < t < 3 ms, again only one input is HIGH, so output will be HIGH.

Thus option (d) is correct.

To solve this kind of problems, you should read about the "Truth Table" of each seven logic gates i.e:-

Universal Logic Gates:- NAND and NOR, called universal since all other can be implimented by these two alone.

Then Logic Gates:- AND, OR, NOT, EX-OR and EX-NOR.

Also take a look of the "Timing Diagram" for graphical concept.

Be feel free to ask doubt in comment section, if any. Thanks.

Related Questions

Navigate

• Browse (All)
• Browse W
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.