Academic Integrity: tutoring, explanations, and feedback — we don’t complete graded work or submit on a student’s behalf.

Use back pages for your SCRATCHES Problem 1 (15 Points) Encircle your answers of

ID: 2266513 • Letter: U

Question

Use back pages for your SCRATCHES Problem 1 (15 Points) Encircle your answers of the following questions: (1.5 point each) T= True; F= False 1. If a 100 MHz frequency is applied to the input CLOCK of a JK flip-flop with J-K-1. the frequency be at the output Q a) 50 MHz b) 25MHz c 12.5 MHz d) 100 MHz 2-* Latch circuit needs a CLOCK Sequential circuits contain memory and combinational circuits do not a) FF b) FT c) TF d) TT 3- Flip-Flops are mainly used for shifting, counting and storing d ** Assume that a J-K flip-flop is used; the output Q is equal to 0 when l=1 and Kl. b) FT d) TT c) TF 4- *The output in Mealy Machine is changed only when the clock edge-triggering has occu "A PAL can be viewed as a programmable AND array and programmable OR array. b) FT d) TT flip-flop is constructed from JK flip-flop, which one of the following is true? c)): D. and K= D S- When a D a)I= D and K-D' b))= K= D 6- How many flip-flops are required to count up to 25610 a) 7 b) 8 d) 256 7-Assume that the combinational circuit of Moore machine produces a delay n ps, the clock period of the sequential circuit must be e) n = n 8- Assume that the control signal Preset and Clear are active LOw in the SR latch, the output Q is valid when Preset and Clear are respectively: a) 00 b) 01 c) 10 d) 11 9- An asynchronous Reset used in an 4 bits counter, where the clock is working in the rising- edge, the output is 0000 when a) Reset is active c) Reset is not active b) Reset is active and Rising edge of Colck d) Reset is not active and Rising edge of Colck 10-A JK latch is realized using a) 2 NORS b) 4 NORs c) 5 NORS d) 6 NORS

Explanation / Answer

The output frequency expression of Jk-flip flop is, f/2.

Therefore, the correct answer is 50 MHz, Option a.