1. (2pts) What is the approximate size of a SiO2 molecule? 2. (2pts) Wafer scale
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1. (2pts) What is the approximate size of a SiO2 molecule? 2. (2pts) Wafer scale integration refers to using an entire wafer as a die to make a single integrated cuit. What is the major reason that wafer-scale integration has not become a viable approach to making very large integrated circuits? 3. 2 pts) What is the major reason that the transconductance gain, gm, of a bipolar transistor is much larger than the gm of a MOS transistor if they are both biased at the same current levels? (2 pts) Some logic is termed "ratio logic". What is the key feature characterizing ratio logic? 4. 5. (2 pts) Why is Cox for n-channel transistors usually approximately equal to Cox for p-channel transistors in a standard bulk CMOS process?Explanation / Answer
1. The atomic weight is 60.08g/mole with a density of 2.27 g/cm3. and monoisotopic mass of 59.96 DA
2. A single large cylindrical crystal of silicon is produced and then cut into wafers. whcih are then cleaned and polished . A photographic process is used to pattern the surface where material ought to be deposited on top of the wafer and where not to. The desired material is deposited and the photographic mask is removed for the next layer. From then on the wafer is repeatedly processed in this fashion, putting on layer after layer of circuitry on the surface. But this is not easy, since given the flaws on the wafers a single large design printed onto a wafer is difficult to achieve. Methods to handle faulty areas of the wafers through logic should be developed to overcome this issue.
3. For a given value of current level, gm of a MOSFET is directly proprtional to squareroot of Id. But in the case of a BJT, gm is directly proportional to Ic.
4. In case of CMOS the pull up network and the pull down network are complementary to each other, which implies that if the pull up network is active the pull down network is inactive. Since both the networks work independently, there is no fight between the pull up network and pull down network to pull up or pull down the output node to Vdd or Gnd respectively. This is not the case in NMOS or pseudo NMOS logic where the pull up network consist of a resistor or a PMOS in linear region both of which has direct path to Vdd. So there is a fight between the pull down and pull up network while pulling the output node to ground. In order to successfully pull down the node to ground the pull down network has to be stronger than the pull up network. Here the word stronger implies that the size of the pull down network must be larger as compared to the pull up network so as to sink more current than the pull up network i.e the ratio of the pull up and pull down networks decides how effectively the output node is pulled down to Gnd. Hence CMOS is ratioless logic while NMOS is a ratioed logic family.
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