1. What is meant by design for testablity (DFT) in VLSI design? 2. Briefy distin
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1. What is meant by design for testablity (DFT) in VLSI design? 2. Briefy distinguish between VLSI design verification and manufacturing test, i.e. what is the purpose of each of them and how are each performed? 3. Briefly describe the impact that rising clock rates and increasing transistor density have on test. Focus your discussion on test complexity and power consumption 4. In design for test, we discussed two types of 'abilities' that are needed to improve "test-ability". What are these? 5. What does BIST mean?Explanation / Answer
1. DFT is a technique, which facilitates a design to become testable after fabrication. “Extra” logic which we put along with the design logic during implementation process, which helps post-production testing. Post-production testing is necessary because, the process of manufacturing is not 100% error free. There are defects in silicon which contribute towards the errors introduced in the physical device. Of course, a chip will not work as per the specifications if there are any errors introduced in fabrication. But the question is how to detect that. Since, to run all the functional tests on each of say a million physical devices, is very time consuming, there was a need for a method, which assures it's maturity without running full exhaustive tests on the physical device in order to ensure that the device has been manufactured correctly.
DFT is a technique which only detects that a fabricated device is faulty or not. After the post-silicon test, if it is found faulty, trash it, don’t ship to customers, on other hand if it is found good, ship it to customers. Since it is a production fault, there is assumed no cure. So it is just a detection, not even a localization of the fault. That is our intended purpose of DFT. For end customer, the DFT logic present on the device is a redundant further justify the need of DFT logic, consider an example where a company needs to provide 1 Million chips to customer. If there isn’t any DFT logic in the chip, and it takes for example, 10 seconds (Its very kind and liberal to take 10 seconds as an example, in fact it can be much longer than that) to test a physical device, then it will take approx. three and a half months just to test the devices before shipping. So the DFT is all about reducing three and a half months to may be three and a half days. Of course practically many testers will be employed to test the chips in parallel to help reducing the test time.
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