VHDL prefered. Design a digital logic circuit which will display using the seven
ID: 2265919 • Letter: V
Question
VHDL prefered. Design a digital logic circuit which will display using the seven digit segment display. (Quartus Altera)
The modes aare as follows:
UP mode the sequence should be 00, 22, 44, 29, 22.
DOWN mode the sequence should be 00, 22, 29, 44, 22.
Also use the LED's to display the current state associating the each state with the specific LED.
Reset is to be connected and will display the first value when activated.
Mode OFF UP DOWN S1 SO 0 I Display the next item in the sequence Description Displayed value should not change 0 Display the previous item in the sequence X- Don't CareExplanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test is
port (
clk : in std_logic;
bcd : in std_logic_vector(3 downto 0); --BCD input
segment7 : out std_logic_vector(6 downto0) -- 7 bit decoded output.
);
end test;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of test is
begin
process (clk,bcd)
BEGIN
if (clk'event and clk='1') then
case bcd is
when "0000"=> segment7 <="0000001"; -- '0'
when "0001"=> segment7 <="1001111"; -- '1'
when "0010"=> segment7 <="0010010"; -- '2'
when "0011"=> segment7 <="0000110"; -- '3'
when "0100"=> segment7 <="1001100"; -- '4'
when "0101"=> segment7 <="0100100"; -- '5'
when "0110"=> segment7 <="0100000"; -- '6'
when "0111"=> segment7 <="0001111"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0000100"; -- '9'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end if;
end process;
end Behavioral;
If you want a decimal number to be displayed using this code then convert the corresponding code into BCD and then instantiate this module for each digit of the BCD code.
Here is a sample test bench code for this module:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
ENTITY test_tb IS
END test_tb;
ARCHITECTURE behavior OF test_tb IS
signal clk : std_logic := '0';
signal bcd : std_logic_vector(3 downto 0) :=(others => '0');
signal segment7 : std_logic_vector(6 downto0);
constant clk_period : time := 1 ns;
BEGIN
uut: entity work.test PORT MAP(clk,bcd,segment7);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc: process
begin
for i in 0 to 9 loop
bcd <= conv_std_logic_vector(i,4);
wait for 2 ns;
end loop;
end process;
END;
}
}
Related Questions
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.