in a common source configuration under self bias conditions. Part 2 will demonst
ID: 2250282 • Letter: I
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in a common source configuration under self bias conditions. Part 2 will demonstrate the characteristic response of an n channel Junction Field Effect Transistor (UFET) in a common source configuration under Voltage Divider bias conditions Components: 2N5458 (or 2N5485 for Multisim), potentiometer, 1/8W resistors, breadboard, wires, Equipment: variable dc power, DMM, oscilloscope, Multisim Procedure: Part 1) Self Bias JFET Pre-Lab Consider a 4-resistor biasing of a JFET. If, instead of using a voltage divider to set a constant voltage as the power source for the gate, we simply consider a zero voltage power source for it, then we end up with a simplified version of the 4-resistor biasing which is called self bias configuration. This naming stems from the fact that the resistor in the source will set up the drain-source current. Do not forget that the self bias configuration is just a simplified version of the more general 4 resistor configuration. But, it is much easier to design since we deal with just one transistor to set up the desired operating point. The self bias configuration is shown in Figure 1. De sign a common source self blas configuration circuit using a 2N5485 n channel Junction Field Effect Transistor (JFET) with the specification given or obtained as follows. Obtain loss and Vosem from the transistor datasheet. [3 points) lass = Place the drain reference voltage, Voo, at +15 Vdc and VGstolf the source reference voltage, Vss, at ground O Vdc. ·Choose gate resistor RG as 1 M (just for electrostatic protection, or protecting against any positive gate-source voltage by mistake). Choose a 2 K potentiometer as Rs Calculate a value for Ro such that for 1: 3 mA, Vo will be 9 volts. Write down your calculations below 13 points) Ro Ro Rs vss Figure 1 Fill the Design row of Table 1 with the results of your design.Explanation / Answer
For, 2N5485 JFET data sheet consists of
IDSS = 4 to 10 mA
VGS(off) = -0.5 to -4,0 V
parameters of the given circuit are
VDD = 15 V; Vss = 0V; Rs = 2000 ohms;RG = 10^6 ohms; ID = 3mA ;VD = 9V
Apply KVL at the Drain of JFET
RD = (VDD - VD) / ID = (15 - 9)/3 = 2000ohms
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