Traffic Light Controller A busy road intersection has two roads, a major road an
ID: 2250177 • Letter: T
Question
Traffic Light Controller
A busy road intersection has two roads, a major road and a minor road. A traffic light controller is to be designed to properly operate the traffic lights. The normal or idle state of the controller is the major road green light on and the minor road red light on.
The minor road has vehicle sensors that send a 1 to the controller when a vehicle is detected. When the sensor is 1, the major road lights sequence from green to yellow and then to red, while the minor road lights go from red to yellow to green in accordance with the timing specifications shown in Table 1.
State
Major Road
Minor Road
Delay (sec)
Idle
Green
Red
Infinite
S0
Green
Red
10
S1
Yellow
Red
2
S2
Red
Red
2
S3
Red
Green
5
S4
Red
Yellow
2
S5
Red
Red
2
Design and implement the controller in VHDL.
Example of simulation results.
A partial sample program for a traffic light controller without a sensor is shown
entity TF_light_controller is
Port ( sensor : in STD_LOGIC;
clk : in STD_LOGIC; reset
: in STD_LOGIC;
major_road : out STD_LOGIC_VECTOR (2 downto 0); --Red Yellow Green
minor_road : out STD_LOGIC_VECTOR (2 downto 0)); -- Red Yellow Green
end TF_light_controller;
architecture Behavioral of TF_light_controller is
signal delay: std_logic_vector(3 downto 0);
constant delay_5: STD_LOGIC_VECTOR(3 downto 0) := "1111"; --5 second delay equivalent to
15 clock pulses
constant delay_1: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- 1 second delay equivalent to
3 clock pulses
type state is (S0,S1,S2,S3, S4,S5);
signal next_state: state;
begin
process (clk, reset) begin
if reset ='1' then next_state <= S0; --green on major road, red on
minor road else if(clk'event and clk ='1') then
case next_state
is when s0 =>
if delay < delay_5 then
next_state <= S0;
delay <= delay + 1;
else next_state <= S1;
delay <= "0000";-- hexadecimal for 0000
is X"0" end if;
when S1 =>
if delay < delay_1 then
next_state <= S1;
delay <= delay + 1;
else next_state <=
S2; delay <= X"0";
end if;
when S2 =>
Insert other case statements here
when others => next_state <= S0;
end case;
end if;
end process;
process(next_state)
begin
case next_state is
when S0 => major_road <= "001"; minor_road <= "100"; --red yellow green sequence
Insert other states here
when others => major_road <= "001"; minor_road <= "100";
end case;
end process;
end Behavioral;
A test bench for the controller with a sensor is shown below. This is to be used to test your design.
entity traffic_tb is
-- Port ( );
end traffic_tb;
architecture Behavioral of traffic_tb is
component TF_light_controller
Port ( sensor : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
major_road : out STD_LOGIC_VECTOR (2 downto 0); --Red Yellow Green
minor_road : out STD_LOGIC_VECTOR (2 downto 0)); -- Red Yellow Green
end component;
--Inputs
signal sensor : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--outputs
signal major_road : std_logic_vector (2 downto 0);
signal minor_road : std_logic_vector (2 downto 0);
--clock period
constant clk_period : time := 100 ns; --delay of 1 sec is 3 times period and 5 sec delay is 5 times
begin
UUT: TF_light_controller PORT MAP (sensor => sensor, clk => clk, reset => reset, major_road => major_road, minor_road => minor_road);
clk_process :process
begin
clk <= '0';
wait for clk_period/2; clk <= '1';
wait for clk_period/2; end process;
--stimulus to test design starts here
stim_proc: process
begin
wait for 1000 ns;
reset <= '1'; sensor <='0'; --then controller should be in idle with major red and minor green
wait for 1000 ns;
reset <= '0'; sensor <='1'; --car on minor road detected then go to state S) to begin change
wait for 2000 ns;
sensor <='0';
wait for 4000 ns;
sensor <= '1';
wait for 2000 ns;
sensor <= '0'; wait;
end process;
end Behavioral;
State
Major Road
Minor Road
Delay (sec)
Idle
Green
Red
Infinite
S0
Green
Red
10
S1
Yellow
Red
2
S2
Red
Red
2
S3
Red
Green
5
S4
Red
Yellow
2
S5
Red
Red
2
SIMULATION-Dehaviora Simuaicn- Functional sim 1 -raflic_tb Untitied 9 Naine Value IIUL resel 0 clko 100000 psExplanation / Answer
-- VHDL project: VHDL code for traffic light controller
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Traffic ligh system for a intersection between highway and farm way
-- There is a sensor on the farm way side, when there are vehicles,
-- Traffic light turns to YELLOW, then GREEN to let the vehicles cross the highway
-- Otherwise, always green light on Highway and Red light on farm way
entity traffic_light_controller is
port ( sensor : in STD_LOGIC; -- Sensor
clk : in STD_LOGIC; -- clock
rst_n: in STD_LOGIC; -- reset active low
light_highway : out STD_LOGIC_VECTOR(2 downto 0); -- light outputs of high way
light_farm: out STD_LOGIC_VECTOR(2 downto 0)-- light outputs of farm way
--RED_YELLOW_GREEN
);
end traffic_light_controller;
architecture traffic_light of traffic_light_controller is
signal counter_1s: std_logic_vector(27 downto 0):= x"0000000";
signal delay_count:std_logic_vector(3 downto 0):= x"0";
signal delay_10s, delay_3s_F,delay_3s_H, RED_LIGHT_ENABLE, YELLOW_LIGHT1_ENABLE,YELLOW_LIGHT2_ENABLE: std_logic:='0';
signal clk_1s_enable: std_logic; -- 1s clock enable
type FSM_States is (HGRE_FRED, HYEL_FRED, HRED_FGRE, HRED_FYEL);
-- HGRE_FRED : Highway green and farm red
-- HYEL_FRED : Highway yellow and farm red
-- HRED_FGRE : Highway red and farm green
-- HRED_FYEL : Highway red and farm yellow
signal current_state, next_state: FSM_States;
begin
-- next state FSM sequential logic
process(clk,rst_n)
begin
if(rst_n='0') then
current_state <= HGRE_FRED;
elsif(rising_edge(clk)) then
current_state <= next_state;
end if;
end process;
-- FSM combinational logic
process(current_state,sensor,delay_3s_F,delay_3s_H,delay_10s)
begin
case current_state is
when HGRE_FRED => -- When Green light on Highway and Red light on Farm way
RED_LIGHT_ENABLE <= '0';-- disable RED light delay counting
YELLOW_LIGHT1_ENABLE <= '0';-- disable YELLOW light Highway delay counting
YELLOW_LIGHT2_ENABLE <= '0';-- disable YELLOW light Farmway delay counting
light_highway <= "001"; -- Green light on Highway
light_farm <= "100"; -- Red light on Farm way
if(sensor = '1') then -- if vehicle is detected on farm way by sensors
next_state <= HYEL_FRED;
-- High way turns to Yellow light
else
next_state <= HGRE_FRED;
-- Otherwise, remains GREEN ON highway and RED on Farm way
end if;
when HYEL_FRED => -- When Yellow light on Highway and Red light on Farm way
light_highway <= "010";-- Yellow light on Highway
light_farm <= "100";-- Red light on Farm way
RED_LIGHT_ENABLE <= '0';-- disable RED light delay counting
YELLOW_LIGHT1_ENABLE <= '1';-- enable YELLOW light Highway delay counting
YELLOW_LIGHT2_ENABLE <= '0';-- disable YELLOW light Farmway delay counting
if(delay_3s_H='1') then
-- if Yellow light delay counts to 3s,
-- turn Highway to RED,
-- Farm way to green light
next_state <= HRED_FGRE;
else
next_state <= HYEL_FRED;
-- Remains Yellow on highway and Red on Farm way
-- if Yellow light not yet in 3s
end if;
when HRED_FGRE =>
light_highway <= "100";-- RED light on Highway
light_farm <= "001";-- GREEN light on Farm way
RED_LIGHT_ENABLE <= '1';-- enable RED light delay counting
YELLOW_LIGHT1_ENABLE <= '0';-- disable YELLOW light Highway delay counting
YELLOW_LIGHT2_ENABLE <= '0';-- disable YELLOW light Farmway delay counting
if(delay_10s='1') then
-- if RED light on highway is 10s, Farm way turns to Yellow
next_state <= HRED_FYEL;
else
next_state <= HRED_FGRE;
-- Remains if delay counts for RED light on highway not enough 10s
end if;
when HRED_FYEL =>
light_highway <= "100";-- RED light on Highway
light_farm <= "010";-- Yellow light on Farm way
RED_LIGHT_ENABLE <= '0'; -- disable RED light delay counting
YELLOW_LIGHT1_ENABLE <= '0';-- disable YELLOW light Highway delay counting
YELLOW_LIGHT2_ENABLE <= '1';-- enable YELLOW light Farmway delay counting
if(delay_3s_F='1') then
-- if delay for Y
VHDL Testbench code for traffic light controller:
-- VHDL projects, Verilog projects
-- VHDL project: VHDL code for traffic light controller
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Testbench VHDL code for traffic light controller
ENTITY tb_traffic_light_controller IS
END tb_traffic_light_controller;
ARCHITECTURE behavior OF tb_traffic_light_controller IS
-- Component Declaration for the traffic light controller
COMPONENT traffic_light_controller
PORT(
sensor : IN std_logic;
clk : IN std_logic;
rst_n : IN std_logic;
light_highway : OUT std_logic_vector(2 downto 0);
light_farm : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
signal sensor : std_logic := '0';
signal clk : std_logic := '0';
signal rst_n : std_logic := '0';
--Outputs
signal light_highway : std_logic_vector(2 downto 0);
signal light_farm : std_logic_vector(2 downto 0);
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the traffic light controller
trafficlightcontroller : traffic_light_controller PORT MAP (
sensor => sensor,
clk => clk,
rst_n => rst_n,
light_highway => light_highway,
light_farm => light_farm
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc: process
begin
rst_n <= '0';
sensor <= '0';
wait for clk_period*10;
rst_n <= '1';
wait for clk_period*20;
sensor <= '1';
wait for clk_period*100;
sensor <= '0';
wait;
end process;
END;
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