How would I actually implement this on a FPGA board with proper LEDs, switches,

Question

How would I actually implement this on a FPGA board with proper LEDs, switches, and a 7-segment display?

Solution: library IEEE; use IEEE.STD LOGIC_1164_STD.ALL; use IEEE.NUMERIC STD ALL; entity top is port (SW :in BIT_VECTOR (3 downto 0); LED out BIT VECTOR (3 downto 0); Segment a out BIT; Segment b out BIT Segment c out BIT Segment d out BIT Segment e out BIT; Segment f out BIT; Segment g out BIT); end entity entity Days_In_Month is port ( I MONTH O DAYS_IN_MONTH : out unsigned(4 downto 0) in unsigned(3 downto 0); end entity Days_In Month; architecture Days In Month combinatorial of Davs In Month is signal month 30d:std_logic; signal month 28d std logic; signal month_31d:std_logic; signal month_29d std logic;

Explanation / Answer

One approach to make date and time accessible is through a consequently created VHDL bundle like the underneath:

library ieee;

utilize ieee.std_logic_1164.all;

bundle datetime is

- Date data

steady YEAR_INT : number := 2013;

steady YEAR_HEX : std_logic_vector(15 downto 0) := X"2013";

steady MONTH_INT : number := 08;

steady MONTH_HEX : std_logic_vector(7 downto 0) := X"08";

steady DAY_INT : number := 09;

steady DAY_HEX : std_logic_vector(7 downto 0) := X"09";

steady DATE_HEX : std_logic_vector(31 downto 0) := YEAR_HEX and MONTH_HEX and DAY_HEX;

- Time data

steady HOUR_INT : whole number := 13;

steady HOUR_HEX : std_logic_vector(7 downto 0) := X"13";

steady MINUTE_INT : whole number := 06;

steady MINUTE_HEX : std_logic_vector(7 downto 0) := X"06";

steady SECOND_INT : whole number := 29;

steady SECOND_HEX : std_logic_vector(7 downto 0) := X"29";

steady TIME_HEX : std_logic_vector(31 downto 0) := X"00" and HOUR_HEX and MINUTE_HEX and SECOND_HEX;

- Miscellaneous data

steady EPOCH_INT : whole number := 1376046389; - Seconds since 1970-01-01_00:00:00

end bundle;

This VHDL bundle can be made with a Tcl content this way:

# Make datetime.vhd bundle from Tcl content

# Current date, time, and seconds since age

# Array file 0 1 2 3 4 5 6

set datetime_arr [clock design [clock seconds] - arrange {%Y %m %d %H %M %S %s}]

# Write VHDL bundle

set filename datetime.vhd

set document [open $filename w]

puts $file "library ieee;"

puts $file "utilize ieee.std_logic_1164.all;"

puts $file ""

puts $file "bundle datetime is"

puts $file " - Date data"

puts $file " consistent YEAR_INT : number := [lindex $datetime_arr 0];"

puts $file " consistent YEAR_HEX : std_logic_vector(15 downto 0) := X"[lindex $datetime_arr 0]";"

puts $file " consistent MONTH_INT : number := [lindex $datetime_arr 1];"

puts $file " consistent MONTH_HEX : std_logic_vector(7 downto 0) := X"[lindex $datetime_arr 1]";"

puts $file " consistent DAY_INT : number := [lindex $datetime_arr 2];"

puts $file " consistent DAY_HEX : std_logic_vector(7 downto 0) := X"[lindex $datetime_arr 2]";"

puts $file " consistent DATE_HEX : std_logic_vector(31 downto 0) := YEAR_HEX and MONTH_HEX and DAY_HEX;"

puts $file " - Time data"

puts $file " consistent HOUR_INT : number := [lindex $datetime_arr 3];"

puts $file " consistent HOUR_HEX : std_logic_vector(7 downto 0) := X"[lindex $datetime_arr 3]";"

puts $file " consistent MINUTE_INT : number := [lindex $datetime_arr 4];"

puts $file " consistent MINUTE_HEX : std_logic_vector(7 downto 0) := X"[lindex $datetime_arr 4]";"

puts $file " consistent SECOND_INT : number := [lindex $datetime_arr 5];"

puts $file " consistent SECOND_HEX : std_logic_vector(7 downto 0) := X"[lindex $datetime_arr 5]";"

puts $file " steady TIME_HEX : std_logic_vector(31 downto 0) := X"00" and HOUR_HEX and MINUTE_HEX and SECOND_HEX;"

puts $file " - Miscellaneous data"

puts $file " steady EPOCH_INT : whole number := [lindex $datetime_arr 6]; - Seconds since 1970-01-01_00:00:00"

puts $file "end bundle;"

close $file

In Altera Quartus II it is conceivable to influence the stream to run this content before blend, whereby the datetime bundle can be made. This is done in the .qsf record with the line beneath, where the content is named "make_datetime.tcl":

set_global_assignment - name PRE_FLOW_SCRIPT_FILE "quartus_sh:make_datetime.tcl"

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