ELEG 4133 Project 3 Project: BCD Counter Due: Nov 20, 2017 Description: Using Vi
ID: 2249891 • Letter: E
Question
ELEG 4133 Project 3 Project: BCD Counter Due: Nov 20, 2017 Description: Using Vivado VHDL programming, design and build a BCD Counter to increment 0-99 or decrement 99 -0 at "exactly" (as close as possible) 1 second intervals. Display the two digit decimal count on the right most 7-segment LED displays. All other displays should be blank. Use the center pushbutton (BTNC) to reset the count to zero. The slide switch O should be placed in the 'on" up position (logic 1) to cause the counter to count and in the "off" down position (logic 0). The slide switch 1 controls the count direction. If switch 1 Is up (logic 1) the counter with count up. If it is down (logic o), the counter will decrement Once the counter code is functional configure the board to load the counter code bit file on power up from a uSB flash memory stick. See the Nexys4-DDR Reference Manual for proper jumper position. The project bit file must be the only bit file in the root (upper level) directory of the memory stick Required devices and software development packages: Nexys4-DDR board Xilinx Vivado Development SystemExplanation / Answer
Counter code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity c09 is
port( rst,clk: in std_logic;
op0,op1,op2,op3: out std_logic_vector(6 downto 0));
end c09;
architecture count of c09 is
component clk_div
Port (
clk : in std_logic;
rst : in std_logic;
op : out std_logic
);
end component;
component segd
port(m: in std_logic_vector(3 downto 0);
num: out std_logic_vector(6 downto 0));
end component;
signal flag: std_logic;
signal a: std_logic_vector(3 downto 0);
signal b: std_logic_vector(3 downto 0);
signal c: std_logic_vector(3 downto 0);
signal d: std_logic_vector(3 downto 0);
begin
c1: clk_div port map(clk,rst,flag);
process(rst,flag)
variable m0: std_logic_vector(3 downto 0):="0000";
variable m1: std_logic_vector(3 downto 0):="0000";
variable m2: std_logic_vector(3 downto 0):="0000";
variable m3: std_logic_vector(3 downto 0):="0000";
begin
if rst='0' then
m0:="0000";
m1:="0000";
m2:="0000";
m3:="0000";
elsif flag'event and flag='1' then
a<=m0;
b<=m1;
c<=m2;
d<=m3;
if m0 /= "1001" then
m0:= m0 + 1;
elsif m0="1001" and m1 /= "1001" then
m0:="0000";
m1:= m1 + 1;
elsif m1="1001" and m2 /= "1001" and m0="1001" then
m1:="0000";
m0:="0000";
m2:= m2 + 1;
elsif m2="1001" and m3/= "1001" and m0="1001" and m1="1001" then
m1:="0000";
m0:="0000";
m2 :="0000";
m3 := m3 + 1;
elsif m3="1001" then
m0:="0000";
m1:="0000";
m2:="0000";
m3:="0000";
end if;
end if;
end process;
z0: segd port map(a,op0);
z1: segd port map(b,op1);
z2: segd port map(c,op2);
z3: segd port map(d,op3);
end count;
seven seg lookup table code:
library ieee;
use ieee.std_logic_1164.all;
entity segd is
port(m: in std_logic_vector(3 downto 0);
num: out std_logic_vector(6 downto 0));
end segd;
architecture sseg of segd is
begin
process(m)
begin
if(m="0000") then
num<="1000000";
elsif(m="0001") then
num<="1111001";
elsif(m="0010") then
num<="0100100";
elsif(m="0011") then
num<="0110000";
elsif(m="0100") then
num<="0011001";
elsif(m="0101") then
num<="0010010";
elsif(m="0110") then
num<="0000010";
elsif(m="0111") then
num<="1111000";
elsif(m="1000") then
num<="0000000";
elsif(m="1001") then
num<="0010000";
else
num<="1111111";
end if;
end process;
end sseg;
most imortant CLOCK CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity clk_div is
Port (
Clk : in std_logic;
rst: in std_logic;
op : out std_logic
);
end clk_div;
architecture RTL of clk_div is
constant max_count : natural := 6000000;
begin
compteur : process(Clk,rst)
variable count : natural range 0 to max_count;
begin
if rst = '0' then
count := 0;
op <= '1';
elsif rising_edge(Clk) then
if count < max_count/2 then
op <='1';
count := count + 1;
elsif count < max_count then
op <='0';
count := count + 1;
else
count := 0;
op <='1';
end if;
end if;
end process compteur;
end RTL;
another way
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity c09 is
port( rst,clk: in std_logic;
op0,op1,op2,op3: out std_logic_vector(6 downto 0));
end c09;
architecture count of c09 is
component clk_div
Port (
clk : in std_logic;
rst : in std_logic;
op : out std_logic
);
end component;
component segd
port(m: in std_logic_vector(3 downto 0);
num: out std_logic_vector(6 downto 0));
end component;
signal flag: std_logic;
signal a: std_logic_vector(3 downto 0);
signal b: std_logic_vector(3 downto 0);
signal c: std_logic_vector(3 downto 0);
signal d: std_logic_vector(3 downto 0);
begin
c1: clk_div port map(clk,rst,flag);
process(rst,flag)
variable m0: std_logic_vector(3 downto 0):="0000";
variable m1: std_logic_vector(3 downto 0):="0000";
variable m2: std_logic_vector(3 downto 0):="0000";
variable m3: std_logic_vector(3 downto 0):="0000";
begin
if rst='0' then
m0:="0000";
m1:="0000";
m2:="0000";
m3:="0000";
elsif flag'event and flag='1' then
a<=m0;
b<=m1;
c<=m2;
d<=m3;
if m0 /= "1001" then
m0:= m0 + 1;
elsif m0="1001" and m1 /= "1001" then
m0:="0000";
m1:= m1 + 1;
elsif m1="1001" and m2 /= "1001" and m0="1001" then
m1:="0000";
m0:="0000";
m2:= m2 + 1;
elsif m2="1001" and m3/= "1001" and m0="1001" and m1="1001" then
m1:="0000";
m0:="0000";
m2 :="0000";
m3 := m3 + 1;
elsif m3="1001" then
m0:="0000";
m1:="0000";
m2:="0000";
m3:="0000";
end if;
end if;
end process;
z0: segd port map(a,op0);
z1: segd port map(b,op1);
z2: segd port map(c,op2);
z3: segd port map(d,op3);
end count;
seven seg lookup table code:
library ieee;
use ieee.std_logic_1164.all;
entity segd is
port(m: in std_logic_vector(3 downto 0);
num: out std_logic_vector(6 downto 0));
end segd;
architecture sseg of segd is
begin
process(m)
begin
if(m="0000") then
num<="1000000";
elsif(m="0001") then
num<="1111001";
elsif(m="0010") then
num<="0100100";
elsif(m="0011") then
num<="0110000";
elsif(m="0100") then
num<="0011001";
elsif(m="0101") then
num<="0010010";
elsif(m="0110") then
num<="0000010";
elsif(m="0111") then
num<="1111000";
elsif(m="1000") then
num<="0000000";
elsif(m="1001") then
num<="0010000";
else
num<="1111111";
end if;
end process;
end sseg;
most imortant CLOCK CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity clk_div is
Port (
Clk : in std_logic;
rst: in std_logic;
op : out std_logic
);
end clk_div;
architecture RTL of clk_div is
constant max_count : natural := 6000000;
begin
compteur : process(Clk,rst)
variable count : natural range 0 to max_count;
begin
if rst = '0' then
count := 0;
op <= '1';
elsif rising_edge(Clk) then
if count < max_count/2 then
op <='1';
count := count + 1;
elsif count < max_count then
op <='0';
count := count + 1;
else
count := 0;
op <='1';
end if;
end if;
end process compteur;
end RTL;
another way
use IEEE.std_logic_unsigned;
-- pin 86 selector de display 1
-- pin 87 selec2 display
-- Seg A pin 85, Seg B 84, Seg C 83, D 82, E 81, F 78, Seg g pin 77, H 76
entity ContadorExamen is
port(
CLK : in std_logic; -- se le asigna el pin 12
--clk1hz : out std_logic ;-- se le asigna el pin 51
datos : out std_logic_vector (6 downto 0);
unidades : out std_logic;
decenas: out std_logic
);
end entity;
architecture BH_Examen2Parcial of ContadorExamen is
signal freq1 : integer range 0 to 5000 := 0;
signal freqDec : integer range 0 to 24999999 := 0;
signal freq100 : integer range 0 to 249999999 := 0;
signal tmp1 : std_logic := '0';
signal tmp100 : std_logic := '0';
signal tmpDec : std_logic := '0';
signal counterUnidades : integer range 0 to 10 := 0;
signal counterDecenas : integer range 0 to 10 := 0;
signal segDecenas : std_logic_vector(6 downto 0);
signal segUnidades : std_logic_vector(6 downto 0);
begin
process(CLK) is
begin
if(CLK'event and CLK = '1') then
if(freq1 >= 5000) then
freq1 <= 0;
tmp1 <= not tmp1;
else
freq1 <= freq1 + 1;
tmp1 <= tmp1;
end if;
if(freq100 >= 249999999) then
freq100 <= 0;
tmp100 <= not tmp100;
else
freq100 <= freq100 + 1;
tmp100 <= tmp100;
end if;
if(freqDec >= 24999999) then
freqDec <= 0;
tmpDec <= not tmpDec;
else
freqDec <= freqDec + 1;
tmpDec <= tmpDec;
end if;
end if;
end process;
-- principio de cambios en el programa
process(tmp1) is
begin
if(tmp1 = '1') then
unidades <= '0';
decenas <= '1';
datos <= segDecenas;
else
datos <= SegUnidades;
decenas <= '0';
unidades <= '1';
end if;
end process;
ParaContarUnidades:process(tmp100) is
begin
if (tmp100 = '1') then
if(counterUnidades = 0) then
segUnidades <= "0000001";
elsif (counterUnidades = 1 ) then
segUnidades <= "1001111";
elsif (counterUnidades = 2 ) then
segUnidades <= "0010010";
elsif (counterUnidades = 3 ) then
segUnidades <= "0000110";
elsif (counterUnidades = 4 ) then
segUnidades <= "1001100";
elsif (counterUnidades = 5 ) then
segUnidades <= "0100100";
elsif (counterUnidades = 6 ) then
segUnidades <= "1100000";
elsif (counterUnidades = 7 ) then
segUnidades <= "0001111";
elsif (counterUnidades = 8 ) then
segUnidades <= "0000000";
elsif (counterUnidades = 9) then
segUnidades <= "0001100";
else
segUnidades <= "1111111";
end if;
if(counterUnidades < 9) then
counterUnidades <= counterUnidades + 1;
else
counterUnidades <= 0;
end if;
end if;
end process;
ParaContarDecenas:process(tmpDec) is
begin
if (tmpDec = '1') then
if(counterDecenas = 0) then
segDecenas <= "0000001";
elsif (counterDecenas = 1 ) then
segDecenas <= "1001111";
elsif (counterDecenas = 2 ) then
segDecenas <= "0010010";
elsif (counterDecenas = 3 ) then
segDecenas <= "0000110";
elsif (counterDecenas = 4 ) then
segDecenas <= "1001100";
elsif (counterDecenas = 5 ) then
segDecenas <= "0100100";
elsif (counterDecenas = 6 ) then
segDecenas <= "1100000";
elsif (counterDecenas = 7 ) then
segDecenas <= "0001111";
elsif (counterDecenas = 8 ) then
segDecenas <= "0000000";
elsif (counterDecenas = 9) then
segDecenas <= "0001100";
else
segDecenas <= "1111111";
end if;
if(counterDecenas < 9) then
counterDecenas <= counterDecenas + 1;
else
counterDecenas <= 0;
end if;
end if;
end process;
end architecture;
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