finish this 6-bit counter. i already have testbench and uncomplete code --Testbe

Question

finish this 6-bit counter. i already have testbench and uncomplete code

--Testbench for counter lab NH 1-4-04

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

USE IEEE.STD_LOGIC_TEXTIO.ALL;

USE STD.TEXTIO.ALL;

ENTITY counter_ATB IS

END counter_ATB;

ARCHITECTURE behavior OF counter_ATB IS

FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

--Constands to set period, setup and Clock to out times.

constant period:time:=50 ns;

constant setup:time:=5 ns;

constant clk2out:time:= 5 ns;

COMPONENT counter

PORT(

CLK : IN std_logic;

CE : IN std_logic;

SRST : IN std_logic;

PRE : IN std_logic;

COUNT_OUT : OUT std_logic_vector(5 downto 0);

TC : INOUT std_logic

);

END COMPONENT;

SIGNAL CLK : std_logic:='0';

SIGNAL CE : std_logic;

SIGNAL SRST : std_logic;

SIGNAL PRE : std_logic;

SIGNAL COUNT_OUT : std_logic_vector(5 downto 0);

SIGNAL TC : std_logic;

BEGIN

uut: counter PORT MAP(

CLK => CLK,

CE => CE,

SRST => SRST,

PRE => PRE,

COUNT_OUT => COUNT_OUT,

TC => TC

);

PROCESS -- clock process

BEGIN

CLOCK_LOOP : LOOP

WAIT FOR Period/2;

clk <= not clk;

END LOOP CLOCK_LOOP;

END PROCESS;

main_line_process: PROCESS

VARIABLE TX_OUT : LINE;

VARIABLE TX_ERROR : INTEGER := 0;

PROCEDURE CHECK_COUNT_OUT(

ExpectedCOUNT_OUT : STD_LOGIC_VECTOR (5 DOWNTO 0);

Marker:integer; --Use a unique value for Marker each time this procedure

--is called to allow for text search for the vaule of marker

TimeOfCheck : time

)

IS

VARIABLE TX_STR : String(1 to 4096);

VARIABLE TX_LOC : LINE;

BEGIN

IF (COUNT_OUT /= ExpectedCOUNT_OUT) THEN

write(TX_LOC,string'("Error at location="));

write(TX_LOC, Marker);

write(TX_LOC,string'(" Time="));

write(TX_LOC, TimeOfCheck);

write(TX_LOC,string'(" COUNT_OUT="));

write(TX_LOC, COUNT_OUT);

write(TX_LOC, string'(", Expected = "));

write(TX_LOC, ExpectedCOUNT_OUT);

write(TX_LOC, string'(" "));

TX_STR(TX_LOC.all'range) := TX_LOC.all;

writeline(results, TX_LOC);

Deallocate(TX_LOC);

ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;

TX_ERROR := TX_ERROR + 1;

END IF;

END;

PROCEDURE CHECK_TC(

ExpectedTC : STD_LOGIC;

Marker:integer; --Use a unique value for Marker each time this procedure

--is called to allow for text search for the vaule of marker

TimeOfCheck : time

)

IS

VARIABLE TX_STR : String(1 to 4096);

VARIABLE TX_LOC : LINE;

BEGIN

IF (TC /= ExpectedTC) THEN

write(TX_LOC,string'("Error at location="));

write(TX_LOC, Marker);

write(TX_LOC,string'(" Time="));

write(TX_LOC, TimeOfCheck);

write(TX_LOC,string'(" TC="));

write(TX_LOC, TC);

write(TX_LOC, string'(", Expected = "));

write(TX_LOC, ExpectedTC);

write(TX_LOC, string'(" "));

TX_STR(TX_LOC.all'range) := TX_LOC.all;

writeline(results, TX_LOC);

Deallocate(TX_LOC);

ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;

TX_ERROR := TX_ERROR + 1;

END IF;

END;

BEGIN

--Time is =0 ns

--Set Starting Values

CE <= '1'; --Disable counter

SRST<='1'; --Drive the counter to 000000

PRE<='0'; --Preset is not active

-------------------------

WAIT FOR Period + clk2out; --One Clock period pluse time for data to update

CHECK_COUNT_OUT("000000",111,now); --The counter is in reset

CHECK_TC('0',111,now);

wait until rising_edge(clk); --Get back to the clock edge

wait for period - setup; --Get to the setup time

CE <= '0'; --Enable counter

SRST<='0'; --Release reset. The counter should be operational

for i in 0 to 6 loop --Let the counter run for a while

wait until rising_edge(clk);

end loop;

wait for clk2out;

CHECK_COUNT_OUT("000111",113,now); --We should be at seven counts

CHECK_TC('0',113,now);

for i in 0 to 51 loop --Run the counter up to roll over

wait until rising_edge(clk);

end loop;

wait for clk2out;

CHECK_COUNT_OUT("111011",222,now); -- We should be at roll over

CHECK_TC('1',222,now);

wait until rising_edge(clk); --Get one clock past roll over

wait for clk2out;

CHECK_COUNT_OUT("000000",224,now); --Check that we are back at 0

CHECK_TC('0',224,now);

for i in 0 to 2 loop --A couple of clocks to get away from 0

wait until rising_edge(clk);

end loop;

  

wait for period - setup; --Check the load function

PRE<='1';

wait until rising_edge(clk);

wait for clk2out;

CHECK_COUNT_OUT("010101",225,now); --010101 should be the load value

PRE<='0';

for i in 0 to 5 loop --Gat away from the load check

wait until rising_edge(clk);

end loop;

wait until rising_edge(clk);

wait for clk2out;

SRST<='1'; --This check is to verify that the reset function is synchronous.

wait for period-(setup + clk2out);

wait for period-(setup + clk2out);

SRST<='0'; --SRST is Synchronous.

  

wait until rising_edge(clk);

wait for clk2out;

CHECK_COUNT_OUT("000001",226,now); --The counter should not reset

wait until rising_edge(clk);

--------------------------------------------------------------------------

IF (TX_ERROR = 0) THEN

write(TX_OUT,string'("No errors or warnings"));

writeline(results, TX_OUT);

ASSERT (FALSE) REPORT

"Simulation successful (not a failure). No problems detected. "

SEVERITY FAILURE;

ELSE

write(TX_OUT, TX_ERROR);

write(TX_OUT, string'(

" errors found in simulation"));

writeline(results, TX_OUT);

ASSERT (FALSE) REPORT

"Errors found during simulation"

SEVERITY FAILURE;

END IF;

END PROCESS;

END;

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/05/2014 02:37:27 PM
-- Design Name:
-- Module Name: Counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Counter is
Port ( CLK : in STD_LOGIC;
CE : in STD_LOGIC;
SRST : in STD_LOGIC;
PRE : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (5 downto 0);
TC : inout STD_LOGIC);
end Counter;

architecture Behavioral of Counter is
signal count : std_logic_vector(5 downto 0):=(others =>'0');
begin
process(CLK, PRE, CE)
begin

end process;
end Behavioral;

Port Name CLK In System Clock Clock enable input. Active LOW! When CE=1 the counter remains in its present state. When CE=0 and a ising clock edge is detected, the counter or resets to 0 if SRST=1. CE has no control over the CE In Synchronous reset i resets to "000000" on nsing clock eds nput Active High Counter when CE=0 SRST In Asynchronous preset input Active High Counter presets to "010101" when PRE-1. Works regardless of clock and clock enable inputs PRE In COUNT OUT Out (6 bits) Counter's output value. 6 bits in length The count should normally count from 0 up to “111011” and then return to 0. TC should be when COUNT OUT"111011" otherwise it should remain at 0 TC Out Table 1. Setup inputs and outputs for new VHDL source file Revised Fall 2017 (Vivado 2017.2) Page 2 of 4 ECE 511-Computer Design Lab Lab 6 Counter Lab Tips and Hints: . The counter design should be implemented using nested "if" "elsif "else" statements. Increment/resetpreset the signal "count and not the port COUNT OUT". After the end process command, set COUNT OUT equal to the signal "count lf PRE-1 set "count" to "O1 0101" rising clock edge or checking if CE=0 since the preset is asynchronous and does not depend on the clock enable (CE) signal Note this should not be inside the "if" statement checking for a · · Once a rising edge is detected and the CE-0 (can include both operations on 1 line), if SRST-1 or . You can use the function: rising_edge (clk) in place of clk'event and clk-'1' to detect a rising edge . After the end process" command, set TC based on the value of "count". (If count is equal to . Refer to Pedroni chapter 6 for some simple counter designs. You can also refer to the course notes TC=1 then reset "count" to "000000" as shown in the course notes III 111011 then set TC 1 otherwise set TC-0) IlII for a more detailed counter design with a preset and reset.

Explanation / Answer

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Counter_6_bit is
Port ( CLK : in STD_LOGIC;
   CE : in STD_LOGIC;
   SRST : in STD_LOGIC;
   PRE : in STD_LOGIC;
   COUNT_OUT : out STD_LOGIC_VECTOR (5 downto 0);
   TC : inout STD_LOGIC);
end Counter_6_bit;

architecture Behavioral of Counter_6_bit is

signal count : STD_LOGIC_VECTOR(5 downto 0):=(others =>'0');
signal tc1 : STD_LOGIC := '0';
begin
process(CLK,CE,RST,PRE)
begin
if PRE = '1' then
  cout <= "010101";
else
  if ( CE = '0') then
   if ( CLK = '1' and CLK'event )then  
    if SRT = '1' then
     cout <= "000000";
    else
     if cout = "111011" then
      count <= "00000";
     else
      count <= count + 1;
     end if;
    end if;
   end if;
  end if;
end if;
end process;

if cout = "111011" then
TC <= '1';     
else
TC <= '0';
end if;
COUNT_OUT <= count;
end Behavioral;

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