Question 1 Assume x3x2x1x0 >= y3y2y1y0. How many different pairs of x3x2x1x0 and

Question

Question 1

Assume x3x2x1x0 >= y3y2y1y0. How many different pairs of x3x2x1x0 and y3y2y1y0 are possible for the given values of p3p2p1p0 = 0111 and g3g2g1g0 = 0001?

Question 2

Consider the 64-bit adders constructed by ripple-carry connection of 1-bit full adders. Determine the gate delay of the last carry out bit c64:

Question 3

Consider the 64-bit adders constructed by ripple-carry connection of 1-bit full adders. Determine the AND/OR gate complexity:

192 AND/OR

Question 4

Consider the 64-bit adders constructed by ripple-carry connection of 1-bit full adders. Determine the XOR gate complexity:

Explanation / Answer

We can see for S=0 Mux will send Y3,Y2,Y1,Y0 input to first stage of full adders so the output from first stage will be X + Y,that is nothing but the T.now since S is 0 XOR gate will pass T as it is(see truth table of XOR gate) not taking 2 datasets one by one for S=0 :

1.

    X : 0011

    Y : 0010

----------------

   T : 0101

now,   p0+ = S+T0+P1= 0+1+1=10 , i.e po+ is 0 and 1 is carry(C)

          p1+ = C+T1+P2= 1+0+0=1   ,i.e p1+ is 1 and carry is 0

          p2+ = C+T2+P3= 0+1+0=1   ,i.e p2+ is 1 and carry is 0

          p3+ = C+T3+S = 0+0+0=0   ,i.e p3+ is 0

therefore P+ is (0110).    Ans.

2. Case 2 can be solved same as case 1.

Now for S=1 mux will take Y(Y2,Y1,Y0,S)

3.  

X : 0 0 0 0

Y : 0 0 0 1

-------------

T : 0 0 0 1

now since S=1, XOR gate will invert T ,so that input to second adder stage will be

T` = 1 1 1 0

p0+ = S+ T0` + p1= 1+ 0 + 0 =1

p1+ = carry + T1` + p2 =0+1+0 =1

p2+ = 0 + 1 +0= 1

p3+ =carry + T3`+S = 0 + 1 + 1 =10 ,i.e P3+ is 0 and 1 is overflow and we dont care about that.

therefore p+ =(0111) ans.

4. Case 4 is same as case 3.

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