1) For this problem you will need to turn in Verilog code and a picture of the w

Question

1) For this problem you will need to turn in Verilog code and a picture of the waveform generated by running a test bench. a) Write a Verilog module for the circuit below using a structural style b) Write a Verilog module for the circuit below using a dataflow style c) Write a Verilog testbench that applies all 8 different tests Notes: The waveform may be better captured using the Windows snipping tool rather than printing it out. The tutorial introduced you to QuestaSim, but you may use any Verilog simulation environment (ModelSim or Verilogger may work).

Explanation / Answer

Code:

module full_adder ( x ,y ,z, f );

output f ;
input x ;
input y ;
input z ;

assign f =( (x | y') & z) | (x'&y'&z');

endmodule

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