Please help me create the VHDL code for 6 bit counter as input and out have the

Question

Please help me create the VHDL code for 6 bit counter as input and out have the condition beblow.......

Description System Clock Clock enable input. Active LOW! When CE=1 the counter remains in its present state. When CE-0 and a rising clock edge is detected, the counter increments or resets to 0 if SRST-1. CE has no control over the Port Name Direction CLK In CE reset (PRE Synchronous reset input. Active High. Counter resets to "000000" on rising clock edge when CE-0 Asynchronous preset input. Active High. Counter presets to "010101" when PRE-1. Works regardless of clock and clock enable inputs. Counter's output value. 6 bits in length. The count should normally count from 0 up to "111011" and then return to 0. TC should be T when COUNTOUT: "111011" otherwise it should remain at ‘o". SRST PRE COUNT_OUT Out (6 bits) TC Out - Table 1. Setup inputs and outputs for new VHDL source file.

Explanation / Answer

--=================================================================================================

-- Libraries

--=================================================================================================

LIBRARY IEEE;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

USE IEEE.std_logic_1164.ALL;

--=================================================================================================

-- Entity Declaration

--=================================================================================================

ENTITY Counter_6bit IS

PORT (

srst_i : IN STD_LOGIC;

clk_i : IN STD_LOGIC;

ce_i : IN STD_LOGIC;

pre_i : IN STD_LOGIC;

tc_o : IN STD_LOGIC;

count_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)

);

END Counter_6bit;

--=================================================================================================

-- Architecture Body

--=================================================================================================

ARCHITECTURE Counter_6bit OF Counter_6bit IS

--=================================================================================================

-- Signal Declaration

--=================================================================================================

SIGNAL s_count : STD_LOGIC_VECTOR(5 DOWNTO 0);

BEGIN

--=================================================================================================

-- Output Port Assignment

--=================================================================================================

count_o <= s_count WHEN(pre_i = '0') ELSE "010101";

--=================================================================================================

-- Synchronous Process

--=================================================================================================

PROCESS(srst_i,clk_i,ce_i)

BEGIN

IF (ce_i = '1') THEN

s_count <= s_count;

ELSIF (sys_clk_i = '1' AND sys_clk_i'event) THEN

IF (srst_i = '1') THEN

s_count <= (OTHERS=>'0');

tc_o <= '0';

ELSE

IF (s_count < "111011")

s_count <= s_count + 1;

tc_o <= '1';

ELSE

s_count <= (OTHERS=>'0');

END IF;

END IF;

END IF;

END PROCESS;

--=================================================================================================

-- Component Instantiation

--=================================================================================================

--NA--

END Counter_6bit;

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