Write a behavioral Verilog Design Module for a circuit that possesses 5 inputs a
ID: 2249555 • Letter: W
Question
Write a behavioral Verilog Design Module for a circuit that possesses 5 inputs and 4 outputs. The 5 inputs are mode and A0-A3. The 4 outputs are X0-X3. If mode=0, the circuit will take the input on A0-A3 and shift it 1 bit to the left (the new rightmost bit should be 0) and place this new value on X0-X3. If mode=1, the circuit will take the input on A0-A3 and shift it 1 bit to the right (the new leftmost bit should be 0) and place this new value on X0-X3. A0-A3 and X0-X3 can be each written as 4-bit vectors.
Once the design module is written, write a test bench for the circuit that gives it at least 4 sets of valid test inputs. You may instantiate the design module either how ISE generates it or how the slides show how to instantiate a design module. Either will work.
Explanation / Answer
VERILOG CODE:
module shifting(x, m, a,clk);
output [3:0] x;
input m;
input [3:0] a;
input clk;
reg [3:0] temp;
reg [3:0]x;
initial begin temp[3:0]=a[3:0]; x=4'b0000; end
always @(negedge clk)
begin
if(m==0)
begin
x[0]<=temp[1];
x[1]<=temp[2];
x[2]<=temp[3];
x[3]<=1'b0;
end
if(m==1)
begin
x[0]<=1'b0;
x[1]<=temp[0];
x[2]<=temp[1];
x[3]<=temp[2];
end
end
endmodule
TEST BENCH:
module shiftingtb_v;
// Inputs
reg m;
reg [3:0] a;
reg clk;
// Outputs
wire [3:0] x;
// Instantiate the Unit Under Test (UUT)
shifting uut (
.x(x),
.m(m),
.a(a),
.clk(clk)
);
initial begin
// Initialize Inputs
m = 0;
a = 4'b1011;
clk = 0;
end
always begin
#4 a=4'b0000;
#4 a=4'b0110;
#4 a=4'b1101;
#4 a=4'b0100;
#4 m=1;
#4 a=4'b0110;
#4 a=4'b0111;
#4 a=4'b1100;
#4 a=4'b1111;
end
always #2 clk=~clk;
initial #100 $finish;
endmodule
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