can you please do part 2, I attached all you need to do the code Introduction: T
ID: 2248919 • Letter: C
Question
can you please do part 2, I attached all you need to do the code
Introduction: The objective of this lab is to teach you how to design finite state machines in Verilog. The state machine will control the taillights of a 1965 Ford Thunderbird. There are three lights on each side that operate to indicate left turn, right turn, break, and hazard as shown in figure 1. The lights operate in sequence to indicate left turn or right turn. Figure 2 shows the flashing sequence for left and right turns. RA RB RC Figure 1 Cauveght© 2000by Pyonce Hal. Inc. (b) RA RB RC Figure 2Explanation / Answer
module tailights(clk,rst,left,right,brake,hazard,Lc,Lb,La,Ra,Rb,Rc);
input clk,rst,left,right,brake,hazard;
output reg Lc,Lb,La,Ra,Rb,Rc;
parameter idle=3'b000,
left1=3'b001,
left2=3'b010,
left3=3'b011,
right1=3'b100,
right2=3'b101,
right3=3'b110,
all=3'b111;
reg [2:0] pstate,nstate;
always @(posedge clk)
begin
if(rst)
pstate<=idle;
else
pstate<=nstate;
end
always @(pstate,left,right,brake,hazard)
begin
case(pstate)
idle:begin
if(hazard|brake)
nstate<=all;
else if (right)
nstate<=right1;
else if (left)
nstate<=left1;
else
nstate<=idle;
end
right1:begin
if(hazard|brake)
nstate<=all;
else if (right)
nstate<=right2;
else if (left)
nstate<=left1;
else
nstate<=idle;
end
right2:begin
if(hazard|brake)
nstate<=all;
else if (right)
nstate<=right3;
else if (left)
nstate<=left1;
end
right3:begin
if(hazard|brake)
nstate<=all;
else if (left)
nstate<=left1;
else
nstate<=idle;
end
left1:begin
if(hazard|brake)
nstate<=all;
else if (right)
nstate<=right1;
else if (left)
nstate<=left2;
else
nstate<=idle;
end
left2:begin
if(hazard|brake)
nstate<=all;
else if (right)
nstate<=right1;
else if (left)
nstate<=left3;
else
nstate<=idle;
end
left3:begin
if(hazard|brake)
nstate<=all;
else if (right)
nstate<=right1;
else
nstate<=idle;
end
all:begin
if(!brake|hazard)
nstate<=idle;
end
default:nstate<=idle;
endcase
end
always @(posedge clk)
begin
case(pstate)
idle:{Lc,Lb,La,Ra,Rb,Rc}<=6'b000000;
all:{Lc,Lb,La,Ra,Rb,Rc}<=6'b111111;
right1:{Lc,Lb,La,Ra,Rb,Rc}<=6'b000100;
right2:{Lc,Lb,La,Ra,Rb,Rc}<=6'b000110;
right3:{Lc,Lb,La,Ra,Rb,Rc}<=6'b000111;
left1:{Lc,Lb,La,Ra,Rb,Rc}<=6'b001000;
left2:{Lc,Lb,La,Ra,Rb,Rc}<=6'b011000;
left3:{Lc,Lb,La,Ra,Rb,Rc}<=6'b111000;
endcase
end
endmodule
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