For this lab, you will code a Verilog module to implement the FSM described in t
ID: 2248715 • Letter: F
Question
For this lab, you will code a Verilog module to implement the FSM described in this document. This lab will also require that you use the Seven- Segment Display on the DE0-CV FPGA board. Design Specifications for the FSM Implement the following simple state machine on the DEO-CV FPGA board. This FSM will have 5 states. The clock to this FSM will be provided by yourself using KEY0 (one of the push buttons on the board) . Include a debounce module in your code but do not use it. So you write the code as described in the lecture, but there should be no debounce module instance. I want you to understand this module but it is unnecessary on our board. The transitions from any one state to another are determined by switches 0 through 4 of the board (SWO, SW1, Sw2, Sw3, and SW4as shown in the state diagram below. This will be easier than using pushbuttons for the inputs to switch to states. That means you set the switch and then clock it using KEY0. It really only matters what the switch positions are when the clock edge occurs. NOTE reiterating this use slide switches not pushbuttons for input. Use KEYo for the clock, and generate the clock signal by hand by pushing KEY0. Any input transition not explicitly referenced in the diagram keeps the machine in the same state. Moreover, if two or more switches are asserted simultaneously, no transition should occur. Swo acts as the reset and should reset the FSM to S00 regardless of all other switches or the pushbutton. (note you could use KEY1 pushbutton instead but it isn't clear that would be better)Explanation / Answer
module fsm(
input KEY0, SW0, SW1, SW2, SW3, SW4,
output REG [6:0] HEX0,
output reg [6:0] HEX1,
output reg [6:0] HEX2,
output reg [6:0] HEX3,
output reg [6:0] HEX4,
output reg [2:0] LED_STATE,
output reg[1:0] LEDZ,
output reg[4:0] LEDSW);
REG [2:0] state;
always @( posedge KEY0 )
begin
case( state )
3'b000:
begin
if( SW0 ) state <= 3'b000;
else if(SW1) state <= 3'b001;
end
3'b001:
begin
if( SW2 ) state <= 2'b010;
end
3'b010:
begin
if( SW3 ) state <= 3'b011;
else if (SW1) state <= 3'b010;
end
3'b011:
begin
if( SW4 ) state <= 3'b100;
else if (SW1) state <= 2'b010;
end
3'b100:
begin
if( SW1 ) state <= 3'b010;
end
endcase
end
always @ (state) begin
case (state)
3'b000:
LEDZ= 2'b00;
LEDSW=5’b00001;
3'b001:
LEDZ= 2'b00;
LEDSW=5’b00010;
3'b010:
LEDZ= 2'b00;
LEDSW=5’b00100;
3'b011:
LEDZ= 2'b10;
LEDSW=5’b01000;
3'b100:
LEDZ= 2'b11;
LEDSW=5’b10000;
default:
LEDZ= 2'b00;
endcase
end
end
endmodule
module debouncer(
input KEY0,
input SW0,
output reg SW0_state
);
reg SW0_sync_0;
always @(posedge clk) SW0_sync_0 <= SW0;
reg SW0_sync_1;
always @(posedge KEY0) SW0_sync_1 <= SW0_sync_0;
reg [15:0] SW0_cnt;
always @(posedge clk)
if(SW0_state==SW0_sync_1)
SW0_cnt <= 0;
else
begin
SW0_cnt <= SW0_cnt + 1'b1;
if(SW0_cnt == 16'hffff) SW0_state <= ~SW0_state;
end
endmodule
All modules are designed but HEX display is not incorporated due to time constraints
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