Show complete solutions and work clearly with verilog design source code for mod

Question

Show complete solutions and work clearly with verilog design source code for modules:

Two submodules partA and partB have been designed as two Verilog files partA.v and partB.v, readily available for use. w12] wI1] S y d[o] w10] module partA (x, y, d); input x, y; output reg [1:0] d; module partB(w,s); output s; endmodule input [2:0] w; endmodule The diagram of mycircuit is shown in Fig.2. Write a Verilog file for the top module part of module mycircuit by instantiating modules partA and partB. (20 points) 0w121 y d[0] w[O] Fig.2 mycircuit

Explanation / Answer

module partA (x,y,d);
input x,y;
output reg [1:0] d;
  
always @(x,y)
begin
d[0]<=x ^ y;
d[1]<=x & y;
end
  
endmodule

module partB (w,s);
input [2:0] w;
output s;
  
assign s=w[0]^w[1]^w[2];  
  
endmodule

module mycircuit(X,f);
input [1:0] X;
output f;
  
wire [1:0] A;
  
partA a1 (.x(X[0]),.y(X[1]),.d(A));
partB a2 (.w({1'b0,A[1],A[0]}),.s(f));
  
endmodule

Related Questions

Navigate

• Browse (All)
• Browse S
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.