Verilog–generate and simulate a hierarchical 4 bit adder/subtractor The assignme
ID: 2248435 • Letter: V
Question
Verilog–generate and simulate a hierarchical 4 bit adder/subtractor
The assignment is:
1.write an rtl module the hierarchical adder/subtractor with inputssub, a,b,ci, and outputs z,co ,oflow
a.z is the sum of a [3:0] and b[3:0] with a carry in (ci)
i.a,b and z are signed (2s complement) numbers
b.sub determines addition (sub=0) or subtraction (sub=1)
c. co is the carry out
d.oflow is high if the addition/subtraction caused an overflow condition
e. co and oflow are a little tricky to get the logic correct. Write out a truth table and determine the algebraic equation.
i. When looking at the results in gtkwave, I would recommend setting the data
format to signed decimal for a, b and z.
f. In the test bench, you may consider driving the ci with a signal other than a carry in to implement the subtraction Remember, if you are using this for an 8 bit
adder/subtractor, you would need to drive the ci of the second block with the co or the first. This module could be used multiple times to add/sub larger numbers.
g.The module name is: addsub_rtl
h.This should be in file “addsub_rtl.v” where addsub_rtl is the name of your module
i.This block does not need to be hierarchical but may be
2. generate a test bench in a file called “ addsub_test.v” for the cell including
i.a test statement to compare gate vs behavioral outputs.
ii. Verilog dump file called “addsub.vcd”.
iii.Be sure you have covered all the input/output states of the cell
iv.Hint, use a 9 or 10 bit register to generate stimuli
v.Include a call to your behavioral cell
3.Simulate the cell and verify it has the correct function
4.Write a gate level description using the 1 bit adder cell from the last assignment as an hierarchical module, and the library verilog_gate_lib.v
Place your module in a file named “addsub.v” with a module name of “addsub”
a.Must be hierarchical and use the “add” module from the prior Verilog project
b.Copy the add.v file from the previous project to the current folder and include it when
you run Verilog. Do NOT copy it into the addsub.v file.
c.Again, the oflow is a bit tricky. HINT: generate a truth table looking at the ci/co of the
MSB and the impact on the oflow.
5.Modify behavioral test bench to include both the behavioral and gate
Verify that the gate model matches the behavioral module using a comparison with strobe statements.
Explanation / Answer
module adder_4bit ( a ,b ,sum ,carry );
output [3:0] sum ;
output carry ;
input [3:0] a ;
input [3:0] b ;
wire [2:0]s;
full_adder u0 (a[0],b[0],1'b0,sum[0],s[0]);
full_adder u1 (a[1],b[1],s[0],sum[1],s[1]);
full_adder u2 (a[2],b[2],s[1],sum[2],s[2]);
full_adder u3 (a[3],b[3],s[2],sum[3],carry);
endmodule
DESIGN
module full_adder ( a ,b ,c ,sum ,carry );
output sum ;
output carry ;
input a ;
input b ;
input c ;
assign sum = a ^ b ^ c;
assign carry = (a&b) | (b&c) | (c&a);
endmodule
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