Lines with errors labeled below. ** Error: C:/altera/15.0/Traffic.vhd(39): near
ID: 2248368 • Letter: L
Question
Lines with errors labeled below.
** Error: C:/altera/15.0/Traffic.vhd(39): near "clk": expecting <= or :=
** Error: C:/altera/15.0/Traffic.vhd(49): near "when": expecting END
** Error: C:/altera/15.0/Traffic.vhd(53): near "else": expecting END
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY traffic is
PORT(
clk, clr, S_ns, S_ew: in STD_LOGIC;
lights: out STD_LOGIC_VECTOR (5 downto 0)
);
end traffic;
ARCHITECTURE behavior of traffic is
type state_type is (s0, s1, s2, s3, s4, s5);
signal state: state_type;
signal count: STD_LOGIC_VECTOR(5 downto 0);
constant SEC15: STD_LOGIC_VECTOR(5 downto 0) := "101101";
constant SEC10: STD_LOGIC_VECTOR(5 downto 0) := "011110";
constant SEC2: STD_LOGIC_VECTOR(5 downto 0) := "000110";
constant SEC1: STD_LOGIC_VECTOR(5 downto 0) := "000011";
BEGIN
process(clk, clr, S_ns, S_ew)
begin
if clr = '1' then
state <= s0;
count <= X"0";
elseif clk'event and clk = '1' then -- line 39
case state is
when s0 =>
if count < SEC15 and (not S_ew) then
state <= s0;
count <= count + 1;
else
state <= s1;
count <= X"0";
end if;
when s1 => -- line 49
if count < SEC2 then
state <= s1;
count <= count + 1;
else
state <= s2; -- line 53
count <= X"0";
end if;
when s2 =>
if count < SEC1 then
state <= s2;
count <= count + 1;
else
state <= s3;
count <= X"0";
end if;
when s3 =>
if count < SEC10 and (not S_ns) then
state <= s3;
count <= count + 1;
else
state <= s4;
count <= X"0";
end if;
when s4 =>
if count < SEC2 then
state <= s4;
count <= count + 1;
else
state <= s5;
count <= X"0";
end if;
when s5 =>
if count < SEC1 then
state <= s5;
count <= count + 1;
else
state <= s0;
count <= X"0";
end if;
when others =>
state <= s0;
end case;
end if;
end process;
C2: process(state)
begin
case state is
when s0 => lights <= "100001";
when s1 => lights <= "100010";
when s2 => lights <= "100100";
when s3 => lights <= "001100";
when s4 => lights <= "010100";
when s5 => lights <= "100100";
when others => lights <= "100001";
end case;
end process;
end behavior;
Explanation / Answer
Try this code :
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY traffic is
PORT(
clk, clr, S_ns, S_ew: in STD_LOGIC;
lights: out STD_LOGIC_VECTOR (5 downto 0)
);
end traffic;
ARCHITECTURE behavior of traffic is
type state_type is (s0, s1, s2, s3, s4, s5);
signal state: state_type;
signal count: STD_LOGIC_VECTOR(5 downto 0);
constant SEC15: STD_LOGIC_VECTOR(5 downto 0) := "101101";
constant SEC10: STD_LOGIC_VECTOR(5 downto 0) := "011110";
constant SEC2: STD_LOGIC_VECTOR(5 downto 0) := "000110";
constant SEC1: STD_LOGIC_VECTOR(5 downto 0) := "000011";
BEGIN
process(clk, clr, S_ns, S_ew)
begin
if clr = '1' then
state <= s0;
count <= X"0";
elsif clk'event and clk = '1' then
case (state) is
when s0 =>
if count < SEC15 and (not S_ew) then
state <= s0;
count <= count + 1;
else
state <= s1;
count <= X"0";
end if;
when s1 =>
if count < SEC2 then
state <= s1;
count <= count + 1;
else
state <= s2;
count <= X"0";
end if;
when s2 =>
if count < SEC1 then
state <= s2;
count <= count + 1;
else
state <= s3;
count <= X"0";
end if;
when s3 =>
if count < SEC10 and (not S_ns) then
state <= s3;
count <= count + 1;
else
state <= s4;
count <= X"0";
end if;
when s4 =>
if count < SEC2 then
state <= s4;
count <= count + 1;
else
state <= s5;
count <= X"0";
end if;
when s5 =>
if count < SEC1 then
state <= s5;
count <= count + 1;
else
state <= s0;
count <= X"0";
end if;
when others =>
state <= s0;
end case;
end if;
end process;
C2: process(state)
begin
case state is
when s0 => lights <= "100001";
when s1 => lights <= "100010";
when s2 => lights <= "100100";
when s3 => lights <= "001100";
when s4 => lights <= "010100";
when s5 => lights <= "100100";
when others => lights <= "100001";
end case;
end process;
end behavior;
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